PHN203
Dual N-channel TrenchMOS logic level FET
Rev. 05 — 27 April 2010
Product data sheet
1. Product profile
1.1 General description
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Suitable for high frequency
applications due to fast switching
characteristics
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC converters
Lithium-ion battery applications
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state
resistance
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
amb
= 25 °C; pulsed;
see
Figure 1;
see
Figure 3
T
amb
= 25 °C; pulsed;
see
Figure 2
V
GS
= 10 V; I
D
= 7 A; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
[1]
Min
-
-
-
Typ
-
-
-
Max Unit
30
6.3
2
V
A
W
[1]
Static characteristics
R
DSon
-
24
30
mΩ
Dynamic characteristics
Q
GD
gate-drain charge V
GS
= 10 V; I
D
= 7 A; V
DS
= 15 V;
T
j
= 25 °C; see
Figure 11
-
3
-
nC
[1]
Single device conducting.
NXP Semiconductors
PHN203
Dual N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S1
G1
S2
G2
D2
D2
D1
D1
source1
gate1
source2
gate2
drain2
drain2
drain1
drain1
1
4
S1
G1
S2
G2
mbk725
Simplified outline
8
5
Graphic symbol
D1 D1
D2 D2
SOT96-1 (SO8)
3. Ordering information
Table 3.
Ordering information
Package
Name
PHN203
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
amb
= 70 °C; pulsed; see
Figure 1
T
amb
= 25 °C; pulsed; see
Figure 1;
see
Figure 3
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive
drain-source
avalanche energy
T
amb
= 25 °C; pulsed
t
p
≤
10 µs; pulsed; T
amb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 8.7 A;
V
sup
≤
30 V; unclamped; t
p
= 0.2 ms;
R
GS
= 50
Ω
[1]
[1]
[1]
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≤
150 °C; T
j
≥
25 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
30
30
20
5
6.3
18
2
150
150
2
4.1
37.8
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
t
p
≤
10 µs; pulsed; T
amb
= 25 °C;
see
Figure 3
T
amb
= 25 °C; pulsed; see
Figure 2
[1]
[1]
Source-drain diode
Avalanche ruggedness
[1]
Single device conducting.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
PHN203
Product data sheet
Rev. 05 — 27 April 2010
2 of 13
NXP Semiconductors
PHN203
Dual N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa19
120
P
der
(%)
80
03aa11
40
40
0
0
50
100
150
200
T
amb
(°C)
0
0
50
100
150
200
T
amb
(°C)
Fig 1.
Normalized continuous drain current as a
function of ambient temperature
10
2
I
D
(A)
10
Limit R
DSon
= V
DS
/ I
D
Fig 2.
Normalized total power dissipation as a
function of ambient temperature
03an69
t
p
= 10
μs
1 ms
1
100 ms
DC
10
−1
1s
10 s
10
−2
10
−1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHN203
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 27 April 2010
3 of 13
NXP Semiconductors
PHN203
Dual N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to solder point
thermal resistance from
junction to ambient
mounted on a printed-circuit board;
minimum footprint; see
Figure 4
Conditions
Min
-
-
Typ
-
-
Max
-
62.5
Unit
K/W
K/W
10
3
Z
th(j-a)
(K/W)
10
2
δ
= 0.5
0.2
10
0.1
0.05
0.02
1
single pulse
10
−1
10
−5
03an68
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to ambient as a function of pulse duration
PHN203
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 27 April 2010
4 of 13
NXP Semiconductors
PHN203
Dual N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 8
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 24 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 24 V; V
GS
= 0 V; T
j
= 150 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 7 A; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
V
GS
= 4.5 V; I
D
= 3.5 A; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
V
GS
= 10 V; I
D
= 7 A; T
j
= 150 °C;
see
Figure 9;
see
Figure 10
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
I
S
= 1.25 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 13
I
S
= 2 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 25 V; T
j
= 25 °C
V
DS
= 20 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 12
V
DS
20 V; V
GS
= 0 V; f = 1 MHz; T
j
= 25 °C;
see
Figure 12
V
DS
= 25 V; R
L
= 25
Ω;
V
GS
= 10 V;
R
G(ext)
= 6
Ω;
T
j
= 25 °C
I
D
= 7 A; V
DS
= 15 V; V
GS
= 10 V;
T
j
= 25 °C; see
Figure 11
-
-
-
-
-
-
-
-
-
-
-
-
14.6
2
3
560
125
85
5
6
21
11
0.75
30
-
-
-
-
-
-
-
-
-
-
1
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
Min
27
30
-
0.6
1
-
-
-
-
-
-
-
Typ
-
-
-
-
1.5
-
-
10
10
24
30
40.8
Max
-
-
2.2
-
2
1
10
100
100
30
55
51
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
PHN203
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 27 April 2010
5 of 13
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