PSMN059-150Y
N-channel TrenchMOS standard level FET
Rev. 01 — 5 May 2008
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using
TrenchMOS technology.
1.2 Features
I
Low body Q
r
I
Fast switching
1.3 Applications
I
Industrial DC motor control
I
DC-to-DC converters
I
Class D audio
I
Switched-mode power supplies
1.4 Quick reference data
I
V
DS
≤
150 V
I
R
DSon
≤
59 mΩ
I
I
D
≤
43 A
I
Q
GD
= 9.1 nC (typ)
2. Pinning information
Table 1.
Pin
1, 2, 3
4
mb
Pinning
Description
source (S)
gate (G)
mounting base; connected to drain
(D)
1 2 3 4
mb
D
Simplified outline
Symbol
G
mbb076
S
NXP Semiconductors
PSMN059-150Y
N-channel TrenchMOS standard level FET
3. Ordering information
Table 2.
Ordering information
Package
Name
PSMN059-150Y
LFPAK
Description
plastic single-ended surface-mounted package; 4 leads
Version
SOT669
Type number
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 12.1 A;
t
p
= 0.21 ms; V
DS
≤
150 V; R
GS
= 50
Ω;
V
GS
= 10 V; starting at T
j
= 25
°C
T
mb
= 25
°C;
V
GS
= 10 V; see
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 10 V; see
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
see
Figure 3
T
mb
= 25
°C;
see
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
-
Max
150
150
±20
43
27.7
129
113
+150
+150
52
208
255
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
2 of 12
NXP Semiconductors
PSMN059-150Y
N-channel TrenchMOS standard level FET
120
P
der
(%)
80
003aab937
120
I
der
(%)
80
003aac023
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
P
tot
P
der
=
-----------------------
×
100
%
-
P
tot
(
25°C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
I
D
I
der
=
-------------------
×
100
%
-
I
D
(
25°C
)
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab749
t
p
= 10
µs
10
100
µs
1 ms
DC
1
10 ms
100 ms
10
−1
1
10
10
2
V
DS
(V)
10
3
T
mb
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
3 of 12
NXP Semiconductors
PSMN059-150Y
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 4.
R
th(j-mb)
[1]
Thermal characteristics
Conditions
[1]
Symbol Parameter
Min
-
Typ
-
Max
1.1
Unit
K/W
thermal resistance from junction to mounting base see
Figure 4
Mounted on a printed-circuit board; vertical in still air.
10
Z
th(j-mb)
(K/W)
1
d = 0.5
0.2
10
−1
0.1
0.05
0.02
10
−2
single shot
t
p
P
003aac268
δ
=
t
p
T
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
4 of 12
NXP Semiconductors
PSMN059-150Y
N-channel TrenchMOS standard level FET
6. Characteristics
Table 5.
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown
voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
; see
Figure 9
and
10
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain leakage current
V
DS
= 120 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
G
R
DSon
gate leakage current
gate resistance
drain-source on-state
resistance
V
GS
=
±20
V; V
DS
= 0 V
f = 1 MHz
V
GS
= 10 V; I
D
= 12 A; see
Figure 6
and
8
T
j
= 25
°C
T
j
= 150
°C
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
gate-source plateau voltage
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 12 A; V
GS
= 0 V; see
Figure 13
I
S
= 12 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V
V
DS
= 75 V; R
L
= 3
Ω;
V
GS
= 10 V; R
G
= 5.6
Ω
V
GS
= 0 V; V
DS
= 30 V; f = 1 MHz;
see
Figure 14
I
D
= 12 A; V
DS
= 75 V; V
GS
= 10 V;
see
Figure 11
and
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
27.9
6.3
9.1
4.8
1529
208
66
14.2
42
54.2
11.1
0.9
114
175
-
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
46
101
59
135
mΩ
mΩ
-
-
-
-
-
-
-
1.1
1
100
100
-
µA
µA
nA
Ω
2
1
-
3
-
-
4
-
4.4
V
V
V
150
133
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
PSMN059_150Y_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 May 2008
5 of 12
京公网安备 11010802033920号
EEWORLD
