BLF7G22L-130;
BLF7G22LS-130
Power LDMOS transistor
Rev. 4 — 20 January 2011
Product data sheet
1. Product profile
1.1 General description
130 W LDMOS power transistor for base station applications at frequencies from
2000 MHz to 2200 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
°
C in a common source class-AB production test circuit.
Mode of operation
2-carrier W-CDMA
1-carrier W-CDMA
[1]
[2]
f
(MHz)
2110 to 2170
2110 to 2170
I
Dq
(mA)
950
950
V
DS
(V)
28
28
P
L(AV)
(W)
30
33
G
p
(dB)
18.5
18.5
η
D
(%)
32
33
ACPR
(dBc)
−32
[1]
−39
[2]
Test signal: 3GPP; test model 1; 64 DPCH; PAR = 8.4 dB at 0.01 % probability on CCDF;
carrier spacing 5 MHz.
Test signal: 3GPP; test model 1; 64 DPCH; PAR = 7.2 dB at 0.01 % probability on CCDF.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low R
th
providing excellent thermal stability
Designed for broadband operation (2000 MHz to 2200 MHz)
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent digital pre-distortion capability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for W-CDMA base stations and multi carrier applications in the
2000 MHz to 2200 MHz frequency range
NXP Semiconductors
BLF7G22L-130; BLF7G22LS-130
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
Pinning
Description
drain
gate
source
[1]
Simplified outline
Graphic symbol
BLF7G22L-130 (SOT502A)
1
3
2
2
3
sym112
1
BLF7G22LS-130 (SOT502B)
1
2
3
drain
gate
source
[1]
1
3
2
2
1
3
sym112
[1]
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name Description
BLF7G22L-130
BLF7G22LS-130
-
-
flanged LDMOST ceramic package; 2 mounting holes;
2 leads
earless flanged LDMOST ceramic package; 2 leads
Version
SOT502A
SOT502B
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
I
D
T
stg
T
j
Parameter
drain-source voltage
gate-source voltage
drain current
storage temperature
junction temperature
Conditions
Min
-
−0.5
-
−65
-
Max
65
+13
28
+150
225
Unit
V
V
A
°C
°C
BLF7G22L-130_7G22LS-130
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 20 January 2011
2 of 15
NXP Semiconductors
BLF7G22L-130; BLF7G22LS-130
Power LDMOS transistor
5. Thermal characteristics
Table 5.
Symbol
R
th(j-c)
Thermal characteristics
Parameter
thermal resistance from junction to case
Conditions
T
case
= 80
°C;
P
L
= 30 W
Typ
Unit
0.35 K/W
6. Characteristics
Table 6.
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
Conditions
V
GS
= 0 V; I
D
= 1.5 mA
V
DS
= 10 V; I
D
= 150 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 7.5 A
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 5.25 A
Min Typ
65
1.3
-
25
-
-
-
-
1.8
-
29.5
-
10
0.1
Max Unit
-
2.3
5
-
450
11
V
V
μA
A
nA
S
0.16
Ω
7. Test information
Table 7.
Functional test information
Mode of operation: 2-carrier W-CDMA; PAR = 8.4 dB at 0.01 % probability on the CCDF; 3GPP test
model 1; 64 DPCH; f
1
= 2112.5 MHz; f
2
= 2117.5 MHz; f
3
= 2162.5 MHz; f
4
= 2167.5 MHz;
RF performance at V
DS
= 28 V; I
Dq
= 950 mA; T
case
= 25
°
C; unless otherwise specified; in a
class-AB production test circuit.
Symbol
P
L(AV)
G
p
RL
in
η
D
ACPR
Parameter
average output power
power gain
input return loss
drain efficiency
adjacent channel power ratio
P
L(AV)
= 30 W
P
L(AV)
= 30 W
P
L(AV)
= 30 W
P
L(AV)
= 30 W
Conditions
Min
-
17
-
29
-
Typ Max
30
−15
32
−31
-
−9
-
−28
18.5 -
Unit
W
dB
dB
%
dBc
7.1 Ruggedness in class-AB operation
The BLF7G22L-130 and BLF7G22LS-130 are capable of withstanding a load mismatch
corresponding to VSWR = 10 : 1 through all phases under the following conditions:
V
DS
= 28 V; I
Dq
= 950 mA; P
L
= 130 W (CW); f = 2110 MHz.
BLF7G22L-130_7G22LS-130
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 20 January 2011
3 of 15
NXP Semiconductors
BLF7G22L-130; BLF7G22LS-130
Power LDMOS transistor
7.2 Impedance information
Table 8.
Typical impedance information
I
Dq
= 950 mA; main transistor V
DS
= 28 V.
Z
S
and Z
L
defined in
Figure 1.
f
(MHz)
2050
2140
2230
Z
S
(Ω)
1.3
−
j3.6
1.9
−
j4.2
3.1
−
j4.7
Z
L
(Ω)
2.2
−
j2.6
2.0
−
j2.6
1.9
−
j2.8
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
BLF7G22L-130_7G22LS-130
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 20 January 2011
4 of 15
NXP Semiconductors
BLF7G22L-130; BLF7G22LS-130
Power LDMOS transistor
7.3 1 Tone CW
19
G
p
(dB)
18
(1)
(2)
001aal341
60
η
D
(%)
40
001aal342
(1)
(2)
(3)
17
(3)
16
20
15
14
0
40
80
120
P
L
(W)
160
0
0
40
80
120
P
L
(W)
160
V
DS
= 28 V; I
Dq
= 950 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
V
DS
= 28 V; I
Dq
= 950 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 2.
Power gain as a function of load power;
typical values
0
RL
in
(dB)
−10
Fig 3.
Drain efficiency as a function of load power;
typical values
001aal352
(1)
(2)
−20
(3)
−30
0
10
20
30
40
50
60
P
L
(W)
70
V
DS
= 28 V; I
Dq
= 950 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 4.
Input return loss as a function of load power; typical values
BLF7G22L-130_7G22LS-130
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 20 January 2011
5 of 15
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