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552BD000195BGR

Description
LVDS Output Clock Oscillator, 186.624MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size4MB,80 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

552BD000195BGR Overview

LVDS Output Clock Oscillator, 186.624MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

552BD000195BGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresIT CAN ALSO OPERATE AT 155.52000 MHZ
Maximum control voltage3.3 V
Minimum control voltage
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate80 ppm
frequency stability50%
JESD-609 codee4
Manufacturer's serial number552
Installation featuresSURFACE MOUNT
Nominal operating frequency186.624 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size177.8mm x 127.0mm x 41.91mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Si552
D
U A L
F
R E Q U E N C Y
VCXO (10 M H
Z T O
1.4 GH
Z
)
Features
Available with any-rate output
frequencies from 10–945 MHz and
select frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL, LVDS
& CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN / WAN
Low-jitter clock generation
Optical Modules
Clock and data recovery
Ordering Information:
See page 7.
Description
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and select frequencies to 1400 MHz. Unlike traditional VCXO’s where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si552 IC based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
V
C
1
2
3
6
5
4
V
DD
FS
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK- CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
®
Clock Synthesis
ADC
V
C
FS
GND
Rev. 0.5 7/06
Copyright © 2006 by Silicon Laboratories
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