PIC16C84
EEPROM Memory Programming Specification
This document includes the programming
specifications for the following devices:
• PIC16C84
Pin Diagram
PDIP, SOIC
RA2
RA3
RA4/T0CKI
MCLR
V
SS
RB0/INT
RB1
RB2
RB3
•1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
V
DD
RB7
RB6
RB5
RB4
1.0
PROGRAMMING THE PIC16C84
PIC16C84
The PIC16C84 is programmed using the serial method.
The serial mode will allow the PIC16C84 to be pro-
grammed while in the users system. This allows for
increased design flexibility.
1.1
Hardware Requirements
The PIC16C84 requires one programmable power sup-
ply for V
DD
(4.5V to 5.5V) and a V
PP
of 12V to 14V. Both
supplies should have a minimum resolution of 0.25V.
1.2
Programming Mode
The programming mode for the PIC16C84 allows pro-
gramming of user program memory, data memory, spe-
cial locations used for ID, and the configuration word.
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16C84
During Programming
Pin Name
RB6
RB7
MCLR
V
DD
V
SS
Pin Name
CLOCK
DATA
V
TEST MODE
V
DD
V
SS
Pin Type
I
I/O
P*
P
P
Clock input
Data input/output
Program Mode Select
Power Supply
Ground
Pin Description
Legend: I =Input, O = Output, P = Power
*In PIC16C84, programming high voltage is internally generated. To activate the programming mode, high voltage needs to be applied
to MCLR input. This means that MCLR does not draw any significant current.
©
1996 Microchip Technology Inc.
DS30189D-page 1
This document was created with FrameMaker 4 0 4
PIC16C84
2.0
2.1
PROGRAM MODE ENTRY
User Program Memory Map
2.2
ID Locations
The user memory space extends from 0x0000 to 0x1FFF
(8K), of which 1K (0x0000 - 0x03FF) is physically imple-
mented. In actual implementation the on-chip user pro-
gram memory is accessed by the lower 10-bits of the PC,
with the upper 3-bits of the PC ignored. Therefore if the
PC is greater than 0x3FF, it will wrap around and address
a location within the physically implemented memory.
(See Figure 2-1).
In programming mode the program memory space
extends from 0x0000 to 0x3FFF, with the first half
(0x0000-0x1FFF) being user program memory and the
second half (0x2000-0x3FFF) being configuration mem-
ory. The PC will increment from 0x0000 to 0x1FFF to
0x2000 to 0x3FFF and wrap around to 0x2000 (not to
0x0000). Once in configuration memory, the highest bit of
the PC stays a '1', thus always pointing to the configura-
tion memory. The only way to point to user program mem-
ory is to reset the part and reenter program/verify mode
as described in Section 2.3.
In the configuration memory space, 0x2000-0x200F are
physically implemented. Locations beyond 0x200F will
physically access user memory. (See Figure 2-1).
A user may store identification information (ID) in four ID
locations. The ID locations are mapped in [0x2000 :
0x2003]. It is recommended that the user use only the
four least significant bits of each ID location. In some
devices, the ID locations read-out in a scrambled fashion
after code protection is enabled. For these devices, it is
recommended that ID location is written as “11 1111 1000
bbbb” where 'bbbb' is ID information.
In other devices, the ID locations read out normally, even
after code protection. To understand how the devices
behave, refer to Table 4.3.
To understand the scrambling mechanism after code pro-
tection, refer to Section 4.0.
DS30189D-page 2
©
1996 Microchip Technology Inc.
EEPROM Memory Programming Specification
FIGURE 2-1:
PROGRAM MEMORY MAPPING
0
3FF
400
Implemented
Non-implemented
1FFF
2000
ID Location
ID Location
ID Location
ID Location
Implemented
200F
2010
2000
2001
2002
2003
2004
2005
2006
2007
Non-implemented
Reserved
Reserved
Reserved
Configuration Word
3FFF
©
1996 Microchip Technology Inc.
DS30189D-page 3
PIC16C84
2.3
Program/Verify Mode
The program/verify mode is entered by holding pins
RB6 and RB7 low while raising MCLR pin from V
IL
to
V
IHH
(high voltage). Once in this mode the user pro-
gram memory and the configuration memory can be
accessed and programmed in serial fashion. The mode
of operation is serial, and the memory that is accessed
is the user program memory. RB6 and RB7 are Schmitt
Trigger Inputs in this mode.
The sequence that enters the device into the program-
ming/verify mode places all other logic into the reset
state (the MCLR pin was initially at V
IL
). This means
that all I/O are in the reset state (High impedance
inputs).
2.3.1
SERIAL PROGRAM/VERIFY OPERATION
Therefore, during a read operation the lsb will be trans-
mitted onto pin RB7 on the rising edge of the second
cycle, and during a load operation the lsb will be
latched on the falling edge of the second cycle. A min-
imum 1
µ
s delay is also specified between consecutive
commands.
All commands are transmitted lsb first. Data words are
also transmitted lsb first. The data is transmitted on the
rising edge and latched on the falling edge of the clock.
To allow for decoding of commands and reversal of
data pin configuration, a time separation of at least 1
µ
s
is required between a command and a data word (or
another command).
The commands that are available are:
2.3.1.1
LOAD CONFIGURATION
The RB6 pin is used as a clock input pin, and the RB7
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB6) is cycled six times. Each command bit
is latched on the falling edge of the clock with the least
significant bit (lsb) of the command being input first.
The data on pin RB7 is required to have a minimum
setup and hold time (see AC/DC specifications) with
respect to the falling edge of the clock. Commands that
have data associated with them (read and load) are
specified to have a minimum delay of 1
µ
s between the
command and the data. After this delay, the clock pin is
cycled 16 times with the first cycle being a start bit and
the last cycle being a stop bit. Data is also input and
output lsb first.
After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits in a “data
word”, as described above, to be programmed into the
configuration memory. A description of the memory
mapping schemes of the program memory for normal
operation and configuration mode operation is shown
in Figure 2-1. After the configuration memory is
entered, the only way to get back to the user program
memory is to exit the program/verify test mode by tak-
ing MCLR low (V
IL
).
TABLE 2-1:
COMMAND MAPPING (SERIAL OPERATION)
Command
Mapping (MSB ... LSB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
1
1
1
1
0, data (14), 0
0, data (14), 0
Data
0, data (14), 0
0, data (14), 0
0, data (14), 0
Load Configuration
Load Data for Program Memory
Read Data from Program Memory
Increment Address
Begin Programming
Load Data for Data Memory
Read Data from Data Memory
Bulk Erase Program Memory
Bulk Erase Data Memory
DS30189D-page 4
©
1996 Microchip Technology Inc.
EEPROM Memory Programming Specification
FIGURE 2-2:
PROGRAM FLOW CHART - PIC16C84 PROGRAM MEMORY
Start
Set V
DD
= V
DDp
Program Cycle
Read Data
Command
Increment Address
Command
No
Data Correct?
Yes
All Locations Done?
Yes
Verify all Locations
@ V
DD
min.
No
Report Programming
Failure
Program Cycle
Load Data
Command
Begin Programming
Command
Data Correct?
Yes
Verify all Locations
@ V
DD
max.
No
Report Verify Error
@ V
DD
min.
Wait 10 ms
Data Correct?
Yes
Done
No
Report Verify Error
@ V
DD
max.
©
1996 Microchip Technology Inc.
DS30189D-page 5
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