74HC132D,652 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> 74HC132D,652

74HC132D,652: DescriptionHC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14; Categorylogic logic; File Size184KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

Download Datasheet Parametric Compare View All

74HC132D,652 Overview

HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14

74HC132D,652 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconduc
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOIC
package instruction	SOP, SOP14,.25
Contacts	14
Manufacturer packaging code	SOT108-1
Reach Compliance Code	compli
ECCN code	EAR99
Is Samacsys	N
series	HC/UH
JESD-30 code	R-PDSO-G14
length	8.65 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.004 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	BULK PACK
Peak Reflow Temperature (Celsius)	260
power supply	2/6 V
Prop。Delay @ Nom-Su	31 ns
propagation delay (tpd)	38 ns
Certification status	Not Qualified
Schmitt trigger	YES
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL/PALLADIUM/GOLD (NI/PD/AU)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
Base Number Matches	1

Preview

Download Datasheet

View All

74HC132; 74HCT132

Quad 2-input NAND Schmitt trigger

Rev. 3 — 30 August 2012

Product data sheet

1. General description

The 74HC132; 74HCT132 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard

No. 7A

The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt trigger inputs. This

device features reduced input threshold levels to allow interfacing to TTL logic levels.

Inputs also include clamp diodes that enable the use of current limiting resistors to

interface inputs to voltages in excess of V

. Schmitt trigger inputs transform slowly

changing input signals into sharply defined jitter-free output signals.

The inputs switch at different points for positive and negative-going signals. The difference

between the positive voltage V

T+

and the negative voltage V

T

is defined as the input

hysteresis voltage V

2. Features and benefits



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Applications



Wave and pulse shapers



Astable multivibrators



Monostable multivibrators

74HC132D,652 Related Products

	74HC132D,652	74HC132D/G,118	74HC132D,653	74HC132D/N,118	74HC132DB,112	74HC132DB,118	74HC132PW,112	74HC132PW,118
Description	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14	HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14
series	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH	HC/UH
Number of functions	4	4	4	4	4	4	4	4
Number of terminals	14	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 Cel	125 °C	125 Cel	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 Cel	-40 °C	-40 Cel	-40 °C	-40 °C	-40 °C	-40 °C
surface mount	YES	Yes	YES	Yes	YES	YES	YES	YES
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	DUAL	pair	DUAL	pair	DUAL	DUAL	DUAL	DUAL
Brand Name	NXP Semiconduc	-	NXP Semiconduc	-	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc
Is it Rohs certified?	conform to	-	conform to	-	conform to	conform to	conform to	conform to
Maker	NXP	-	NXP	-	NXP	NXP	NXP	NXP
Parts packaging code	SOIC	-	SOIC	-	SSOP1	SSOP1	TSSOP	TSSOP
package instruction	SOP, SOP14,.25	-	SOP, SOP14,.25	-	SSOP, SSOP14,.3	SSOP, SSOP14,.3	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25
Contacts	14	-	14	-	14	14	14	14
Manufacturer packaging code	SOT108-1	-	SOT108-1	-	SOT337-1	SOT337-1	SOT402-1	SOT402-1
Reach Compliance Code	compli	-	compli	-	compli	compli	compli	compli
Is Samacsys	N	-	N	-	N	N	N	N
JESD-30 code	R-PDSO-G14	-	R-PDSO-G14	-	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
length	8.65 mm	-	8.65 mm	-	6.2 mm	6.2 mm	5 mm	5 mm
Load capacitance (CL)	50 pF	-	50 pF	-	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	NAND GATE	-	NAND GATE	-	NAND GATE	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	0.004 A	-	0.004 A	-	0.004 A	0.004 A	0.004 A	0.004 A
Humidity sensitivity level	1	-	1	-	1	1	1	1
Number of entries	2	-	2	-	2	2	2	2
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	-	SOP	-	SSOP	SSOP	TSSOP	TSSOP
Encapsulate equivalent code	SOP14,.25	-	SOP14,.25	-	SSOP14,.3	SSOP14,.3	TSSOP14,.25	TSSOP14,.25
Package shape	RECTANGULAR	-	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	-	SMALL OUTLINE	-	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	BULK PACK	-	TAPE AND REEL	-	TUBE	TAPE AND REEL	TUBE	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	-	260	-	260	260	260	260
power supply	2/6 V	-	2/6 V	-	2/6 V	2/6 V	2/6 V	2/6 V
Prop。Delay @ Nom-Su	31 ns	-	31 ns	-	31 ns	38 ns	31 ns	38 ns
propagation delay (tpd)	38 ns	-	38 ns	-	38 ns	38 ns	38 ns	38 ns
Certification status	Not Qualified	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	YES	-	YES	-	YES	YES	YES	YES
Maximum seat height	1.75 mm	-	1.75 mm	-	2 mm	2 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	6 V	-	6 V	-	6 V	6 V	6 V	6 V
Minimum supply voltage (Vsup)	2 V	-	2 V	-	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	-	5 V	-	5 V	5 V	5 V	5 V
technology	CMOS	-	CMOS	-	CMOS	CMOS	CMOS	CMOS
Terminal surface	NICKEL/PALLADIUM/GOLD (NI/PD/AU)	-	Nickel/Palladium/Gold (Ni/Pd/Au)	-	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal pitch	1.27 mm	-	1.27 mm	-	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Maximum time at peak reflow temperature	30	-	30	-	30	30	30	30
width	3.9 mm	-	3.9 mm	-	5.3 mm	5.3 mm	4.4 mm	4.4 mm
Base Number Matches	1	-	1	-	1	1	1	1
JESD-609 code	-	-	e4	-	e4	e4	e4	e4

Recommended Resources

Zero-crossing trigger circuit design based on thyristor

Music synchronized lantern controller circuit

Multi-purpose home appliance timing controller circuit

Forward and reverse command switch control for general frequency converters

Improved nickel-cadmium battery automatic charging circuit

Small wireless walkie-talkie circuit diagram

Does anyone know how to initialize the input capture function of GD32?: The following code is the input capture function of GD32F303CBT6 that I wrote according to the information on the Internet. It uses PA0 and TIME4_CH0. The PA0 pin has input a 50% signal of 1KHZ. #incl...; bigbat GD32 MCU

Detailed information about FUTABA S3010: I have collected relatively complete information from the Internet. You can take a look if you need it, and you don't have to look for it everywhere....; 范小川 NXP MCU

Wi-Fi Direct, this technology is quite interesting, who has paid attention to it?: I was looking up information online these days, and suddenly found an interesting technology. Let's take a look at the introduction of the Wi-Fi Alliance: [url=http://www.wi-fi.org/discover-wi-fi/wi-f...; fish001 RF/Wirelessly

Intel SoC FPGA Developer Forum (ISDF) pre-registration and gift-giving event has begun! ! ! (Awards have been awarded): [align=left][color=#000000][url=https://bbs.eeworld.com.cn/thread-506105-1-1.html]This event has been awarded[/url] [/color]After Intel completed the acquisition of Altera, Altera SoC Developer Forum ...; EEWORLD社区 FPGA/CPLD

Use the compiled database file as a connection file to provide to those who need the FPGA module: If you want to keep your design files private for security reasons, you can use the Quartus II database to send someone your full compilation results without sending your source design files. The Quar...; eeleader FPGA/CPLD

EEPROM analysis based on single chip microcomputer: [size=4] In actual applications, the data stored in the MCU RAM will be lost after power failure, and the data stored in the MCU FLASH cannot be changed at will, that is, it cannot be used to record t...; Aguilera Microcontroller MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components