HEF4066B
Quad single-pole single-throw analog switch
Rev. 7 — 16 November 2011
Product data sheet
1. General description
The HEF4066B provides four single-pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON
resistance. In addition the ON resistance is relatively constant over the full input signal
range.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
Specified from
40 C
to +85
C
and
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
HEF4066BP
HEF4066BT
40 C
to +125
C
40 C
to +125
C
Name
DIP14
SO14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT27-1
SOT108-1
Type number
NXP Semiconductors
HEF4066B
Quad single-pole single-throw analog switch
5. Functional diagram
1Y
1E
2Y
2E
3Y
3E
4Y
4E
1
13
4
5
8
6
11
12
2
1Z
nY
3
2Z
nE
9
3Z
V
DD
V
DD
10
4Z
V
SS
001aag200
nZ
001aag201
Fig 1.
Functional diagram
Fig 2.
Logic diagram (one switch)
6. Pinning information
6.1 Pinning
1Y
1Z
2Z
2Y
2E
3E
V
SS
1
2
3
4
5
6
7
001aag202
14 V
DD
13 1E
12 4E
HEF4066B
11 4Y
10 4Z
9
8
3Z
3Y
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Symbol
1Y, 2Y, 3Y, 4Y
1Z, 2Z, 3Z, 4Z
1E, 2E, 3E, 4E
V
SS
V
DD
Pin description
Pin
1, 4, 8, 11
2, 3, 9, 10
13, 5, 6, 12
7
14
Description
independent input or output
independent input or output
enable input (active HIGH)
ground (0 V)
supply voltage
HEF4066B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 16 November 2011
2 of 16
NXP Semiconductors
HEF4066B
Quad single-pole single-throw analog switch
7. Functional description
Table 3.
Input nE
H
L
[1]
Function table
[1]
Switch
ON
OFF
H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
DD
I
IK
V
I
I
I/O
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
input/output current
storage temperature
ambient temperature
total power dissipation
T
amb
=
40 C
to +85
C
DIP14
SO14
P
[1]
[2]
[3]
[1]
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
65
40
-
-
-
Max
+18
10
V
DD
+ 0.5
10
+150
+85
750
500
100
Unit
V
mA
V
mA
C
C
mW
mW
mW
power dissipation
per switch
To avoid drawing V
DD
current out of terminal nZ, when switch current flows into terminals nY, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no V
DD
current will flow out of terminals nY, in this case there
is no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed V
DD
or V
SS
.
For DIP14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 12 mW/K.
For SO14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 8 mW/K.
[2]
[3]
9. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall
rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+125
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
HEF4066B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 16 November 2011
3 of 16
NXP Semiconductors
HEF4066B
Quad single-pole single-throw analog switch
10. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level
input voltage
I
O
< 1
A
5V
10 V
15 V
I
I
I
S(OFF)
input leakage
current
OFF-state
leakage
current
per channel;
see
Figure 4
15 V
15 V
T
amb
=
40 C
T
amb
= 25
C
Min
3.5
7.0
11.0
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
0.1
-
Min
3.5
7.0
11.0
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
0.1
200
T
amb
= 85
C
T
amb
= 125
C
Unit
Min
3.5
7.0
11.0
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
1.0
-
Min
3.5
7.0
11.0
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
1.0
-
V
V
V
V
V
V
A
nA
I
DD
supply current all valid input
combinations
5V
10 V
15 V
-
-
-
-
-
1.0
2.0
4.0
-
-
-
-
-
1.0
2.0
4.0
7.5
-
-
-
-
7.5
15.0
30.0
-
-
-
-
-
7.5
15.0
30.0
-
A
A
A
pF
C
I
input
capacitance
nE input
10.1 Test circuit
V
DD
nE
nZ
VI
V
IL
nY
V
SS
I
S
VO
001aak669
Fig 4.
Test circuit for measuring OFF-state leakage current
HEF4066B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 16 November 2011
4 of 16
NXP Semiconductors
HEF4066B
Quad single-pole single-throw analog switch
10.2 ON resistance
Table 7.
ON resistance
T
amb
= 25
C; I
SW
= 200
A; V
SS
= 0 V.
Symbol
R
ON(peak)
Parameter
ON resistance (peak)
Conditions
V
I
= 0 V to V
DD
; see
Figure 5
and
Figure 6
V
DD
5V
10 V
15 V
R
ON(rail)
ON resistance (rail)
V
I
= 0 V; see
Figure 5
and
Figure 6
5V
10 V
15 V
V
I
= V
DD
; see
Figure 5
and
Figure 6
5V
10 V
15 V
R
ON
ON resistance mismatch
between channels
V
I
= 0 V to V
DD
; see
Figure 5
5V
10 V
15 V
Typ
350
80
60
115
50
40
120
65
50
25
10
5
Max
2500
245
175
340
160
115
365
200
155
-
-
-
Unit
10.2.1 ON resistance waveform and test circuit
001aak671
400
R
ON
(Ω)
300
(1)
V
SW
200
V
DD
nE
100
nY
VI
V
IH
nZ
V
SS
ISW
(2)
(3)
0
0
001aak670
5
10
V
I
(V)
15
R
ON
= V
SW
/ I
SW
.
I
SW
= 200
A.
(1) V
DD
= 5 V
(2) V
DD
= 10 V
(3) V
DD
= 15 V
Fig 5.
Test circuit for measuring R
ON
Fig 6.
Typical R
ON
as a function of input voltage
HEF4066B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 16 November 2011
5 of 16
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