74HC4051-Q100; 74HCT4051-Q100
8-channel analog multiplexer/demultiplexer
Rev. 2 — 8 October 2012
Product data sheet
1. General description
The 74HC4051-Q100; 74HCT4051-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance
with JEDEC standard no. 7A.
The 74HC4051-Q100; 74HCT4051-Q100 is an 8-channel analog
multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable
input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z).
With E LOW, one of the eight switches is selected (low impedance ON-state) by S0 to S2.
With E HIGH, all switches are in the high-impedance OFF-state, independent of S0 to S2.
V
CC
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for 74HC4051-Q100 and 4.5 V to 5.5 V for
74HCT4051-Q100. The analog inputs/outputs (Y0 to Y7, and Z) can swing between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
V
EE
may not exceed 10.0 V. For
operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide analog input voltage range from
5
V to +5 V
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0
)
CDM AEC-Q100-011 revision B exceeds 1000 V
Multiple package options
NXP Semiconductors
74HC4051-Q100; 74HCT4051-Q100
8-channel analog multiplexer/demultiplexer
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4051D-Q100
74HCT4051D-Q100
74HC4051PW-Q100
74HCT4051PW-Q100
74HC4051BQ-Q100
74HCT4051BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16
leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5
3.5
0.85 mm
74HC_HCT4051_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 8 October 2012
2 of 31
NXP Semiconductors
74HC4051-Q100; 74HCT4051-Q100
8-channel analog multiplexer/demultiplexer
5. Functional diagram
V
CC
16
13 Y0
S0 11
14 Y1
15 Y2
S1 10
12 Y3
LOGIC
LEVEL
CONVERSION
S2 9
1-OF-8
DECODER
1 Y4
5 Y5
2 Y6
E 6
4 Y7
3 Z
8
GND
7
V
EE
001aad543
Fig 1.
Functional diagram
74HC_HCT4051_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 8 October 2012
3 of 31
NXP Semiconductors
74HC4051-Q100; 74HCT4051-Q100
8-channel analog multiplexer/demultiplexer
11
10
9
6
0
8X
2
G8
0
7
13
S0
S1
S2
11
10
9
14
15
12
1
5
2
E
6
3
Z
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3
MUX/DMUX
0
1
2
3
4
5
6
7
13
14
15
12
1
5
2
4
001aad541
001aad542
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Y
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
Z
V
EE
001aad544
Fig 4.
Schematic diagram (one switch)
74HC_HCT4051_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 8 October 2012
4 of 31
NXP Semiconductors
74HC4051-Q100; 74HCT4051-Q100
8-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74HC4051-Q100
74HCT4051-Q100
terminal 1
index area
Y6
16 V
CC
15 Y2
14 Y1
13 Y0
12 Y3
11 S0
10 S1
9
aaa-003160
74HC4051-Q100
74HCT4051-Q100
Y4
Y6
Z
Y7
Y5
E
V
EE
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
S2
9
V
CC(1)
16 V
CC
15 Y2
14 Y1
13 Y0
12 Y3
11 S0
10 S1
Z
Y7
Y5
E
V
EE
1
Y4
S2
aaa-003161
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5.
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
E
V
EE
GND
S0, S1, S2
Z
V
CC
Pin description
Pin
6
7
8
11, 10, 9
3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
common output or input
supply voltage
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4 independent input or output
74HC_HCT4051_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 8 October 2012
5 of 31
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