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AS7C164L-12JC

Description
Standard SRAM, 8KX8, 12ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
Categorystorage    storage   
File Size211KB,8 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C164L-12JC Overview

Standard SRAM, 8KX8, 12ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

AS7C164L-12JC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeSOJ
package instructionSOJ, SOJ28,.34
Contacts28
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time12 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J28
JESD-609 codee0
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals28
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ28,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.00006 A
Minimum standby current2 V
Maximum slew rate0.105 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
High Performance
8K×8
CMOS SRAM
AS7C164
AS7C164L
®
8K
×
8 CMOS SRAM (Common I/O)
Features
• Organization: 8,192 words × 8 bits
• High speed
- 8/10/12/15/20 ns address access time
- 3/3/3/4/5 ns output enable access time
• Low power consumption
- Active: 633 mW max (10 ns cycle)
- Standby:11 mW max, CMOS I/O
1.1 mW max, CMOS I/O, L version
• Very low DC component in active power
• 2.0V data retention (L version)
• Equal access and cycle times
• Very fast 3 ns output enable access time
• Easy memory expansion with CE1, CE2, OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
• 300 mil PDIP and SOJ
• ESD protection > 2000 volts
• Latch-up current > 200 mA
Logic block diagram
Vcc
GND
Input buffer
A1
A2
A3
A4
A10
A11
A12
I/O7
128×64×8
Array
(65,536)
Sense amp
Pin arrangement
DIP, SOJ
I/O0
Column decoder
A A A A AA
0 5 6 7 8 9
WE
OE
CE1
CE2
Control
Circuit
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
CE2
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Row decoder
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
L
7C164-8
8
3
120
2.0
-
7C164-10
10
3
115
2.0
0.2
7C164-12
12
3
110
2.0
0.2
7C164-15
15
4
100
2.0
0.2
7C164-20
20
5
90
2.0
0.2
Unit
ns
ns
mA
mA
mA
ALLIANCE SEMICONDUCTOR
AS7C164

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