ADVANCE D COM P ON E NTS PACKAG I NG
512 Megabit CMOS DDR SDRAM
DPDD32MX16WSCY5
DESCRIPTION:
The Memory Stack™ series is a family of interchangeable memory modules. The 512 Megabit Double Data Rate Synchronous
DRAM module is a member of this family which utilizes the space saving LP-Stack™ TSOP stacking technology. The devices
are constructed with two 16 Meg x 16 DDR SDRAMs.
This 256 Megabit based LP-Stack™ module DPDD32MX16WSCY5, has been designed to fit in the same footprint as the 16
Meg x 16 DDR SDRAM TSOP monolithic. This allows system upgrade without electrical or mechanical redesign, providing an
immediate and low cost memory upgrade solution.
PIN-OUT DIAGRAM
FEATURES:
• Configuration:
VDD
1
66 VSS
32M x 16 (2 Banks of 4 Meg x 16 bits x 4 banks)
DQ0
2
65 DQ15
• JEDEC Approved Footprint and Pinout
VDDQ
3
64 VSSQ
DQ1
4
63 DQ14
• IPC-A-610 Manufacturing Standards
DQ2
5
62 DQ13
VSSQ
6
61 VDDQ
• Package: 66-Pin Leaded TSOP Stack
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The following features are not affected by LP-Stack and are
provided as reference only. Refer to memory OEM device
specification for details.
• Clock Frequency is determined by OEM memory
device used.
• 2.5 Volt DQ Supply
• JEDEC Standard SSTL_2 Interface for all
Inputs/Outputs
• Four Bank Operation
• Programmable Burst Type:
Burst Length and Read Latency
• Refresh: Refer to memory OEM specifications
• Auto and Self Refresh
PIN NAMES
A0-A12
BA0,BA1
A10/AP
DQ0-DQ15
CAS
CS0, CS1
RAS
WE
CK, CK
CKE0, CKE1
UDQS, LDQS
UDM, LDM
QFC
V
DD
Vss
V
DDQ
Vss
Q
V
REF
N.C.
NU
30A246-00
REV. D 6/02
Row Address: A0 - A12
Column Address: A0 - A9
Bank Select Address
Auto Precharge
Data In/Data Out
Column Address Strobe
Chip Selects
Row Address Strobe
Data Write Enable
Differential Clock Inputs
Clock Enables
Data Strobe
Data Mask
DQ FET Switch Control
Power Supply (+2.5V)
Ground
DQ Power Supply (+2.5V)
DQ Ground
Reference Voltage for inputs
No Connect
Not Used, Electrical Connect is Present
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
N.C.
VDDQ
LDQS
N.C.
VDD
*NU/QFC
LDM
WE
CAS
RAS
CS0
CS1
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
(TOP VIEW)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
N.C.
VSSQ
UDQS
N.C.
VREF
VSS
UDM
CK
CK
CKE0
CKE1
A12
A11
A9
A8
A7
A6
A5
A4
VSS
* This pin is a No Connect for some Manufacturers.
FUNCTIONAL BLOCK DIAGRAM
CS1
CKE1
CS0
CKE0
RAS
CAS
WE
CK
CK
QFC
VREF
UDQS/LDQS
UDM/LDM
A0-A12
BA0-BA1
(4 Meg x 16 Bits x 4 Banks)
256 Mb DDR SDRAM
(4 Meg x 16 Bits x 4 Banks)
DQ0-DQ15
This document contains information on a product that is currently released to production at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
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512 Megabit CMOS DDR SDRAM
DPDD32MX16WSCY5
MECHANICAL DRAWING
DP
PREFIX
DD
TYPE
32M
MEMORY
DEPTH
X
DESIG
16
MEMORY
WIDTH
W
DESIG
S
I/O TYPE
C
DEVICE
WIDTH
Y5
PACKAGE
- DP - XX
SUPPLIER
MFR ID
XX
CYCLE
TIME
XX
CAS
LATENCY
15
20
25
60
70
75
08
10
CAS LATENCY 1.5
CAS LATENCY 2.0
CAS LATENCY 2.5
6ns (166MHz)
7ns (143MHz)
7.5ns (133MHz)
8ns (125MHz)
10ns (100MHz)
MANUFACTURER CODE *
SUPPLIER CODE *
STACKABLE TSOP
x16 MEMORY BASED
SSTL INPUTS/OUTPUTS
256 MEGABIT BASED
MEMORY MODULE WITHOUT SUPPORT LOGIC
DOUBLE DATA RATE SYNCHRONOUS DRAM
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturer’s specifications.
2. DC Parameters may be affected by stacking. Please refer to Application Note 53A004-00 for further information.
MECHANICAL DRAWING
PIN 1
INDEX
TOP VIEW
1
SIDE VIEW
BOTTOM VIEW
.885±.010
[22.48±.25]
.0256 [.65]
TYP
.015 [.18]
TYP
.102 MAX
[2.59 MAX]
Standard TSOP pad layout is acceptable, however, when possible, the
following pad layout is recommended for optimal manufacture and
inspection. See Application Note 53A001-00 for further information.
.502±.008
[12.75±.20]
.0256 [.65] BSC
.427 [10.85]
.417 [10.59]
.527 [13.39]
.517 [13.13]
END VIEW
.020 [.51]
.016 [.41]
.819 [20.80] BSC
30A246-00
REV. D 6/02
DPAC Technologies
Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841
Tel
714 898 0007
Fax
714 897 1772
www.dpactech.com Nasdaq: DPAC
©2002 DPAC Technologies, all rights reserved. DPAC Technologies™, Memory Stack™, System Stack™, CS Stack™ are trademarks of DPAC Technologies Corp.
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