74HC4020; 74HCT4020
14-stage binary ripple counter
Rev. 5 — 6 August 2012
Product data sheet
1. General description
The 74HC4020; 74HCT4020 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4020B series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4020; 74HCT4020 are 14-stage binary ripple counters with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0, Q3
to Q13). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
2. Features and benefits
Multiple package options
Complies with JEDEC standard no. 7A
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4020N
74HCT4020N
74HC4020D
74HCT4020D
74HC4020DB
74HCT4020DB
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
40 C
to +125
C
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
plastic shrink small outline package; 16 leads; body SOT338-1
width 5.3 mm
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
Table 1.
Ordering information
…continued
Package
Temperature range
Name
TSSOP16
Description
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT403-1
40 C
to +125
C
40 C
to +125
C
Type number
74HC4020PW
74HCT4020PW
74HC4020BQ
74HCT4020BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
CP
MR
10
11
T
14-STAGE COUNTER
C
D
9
7
5
4
6
13
12
14
15
1
2
3
Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
001aal201
Fig 1.
Functional diagram
CTR14
Q0
Q3
Q4
Q5
10
CP
Q6
Q7
Q8
Q9
11
MR
Q10
Q11
Q12
Q13
9
7
5
4
6
13
12
14
15
1
2
3
13
CT
10
11
+
CT = 0
0
9
7
5
4
6
13
12
14
15
1
2
3
001aal202
001aal203
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
2 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
Q
CP
FF
T 1
Q
RD
MR
RD
FF
T 2
Q
FF
T 3
Q
RD
Q
FF
T 4
Q
RD
Q
FF
T 6
Q
RD
Q
Q
Q0
Q3
Q13
001aal204
Fig 4.
Logic diagram
6. Pinning information
6.1 Pinning
74HC4020
74HCT4020
terminal 1
index area
Q12
16 V
CC
15 Q10
14 Q9
13 Q7
12 Q8
11 MR
10 CP
9
001aal205
74HC4020
74HCT4020
Q11
Q12
Q13
Q5
Q4
Q6
Q3
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
Q0
9
V
CC(1)
16 V
CC
15 Q10
14 Q9
13 Q7
12 Q8
11 MR
10 CP
Q13
Q5
Q4
Q6
Q3
1
Q11
Q0
001aal206
Transparent top view
(1) The substrate is attached to this pad using conductive
die attach material. It cannot be used as supply pin or
input. It is recommended that no connection is made at
all.
Fig 5.
Pin configuration DIP16, SO16, SSOP16 and
TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q0, Q3 to Q13
GND
CP
MR
V
CC
74HC_HCT4020
Pin description
Pin
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3
8
10
11
16
Description
output
ground (0 V)
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
3 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
7. Functional description
Table 3.
Input
CP
X
[1]
Function table
Output
MR
L
L
H
Q0, Q3 to Q13
no change
count
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
7.1 Timing diagram
1
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aal207
2
4
8
16
32
64
128
256
512 1024 2048 4096 8192 16384
Fig 7.
Timing diagram
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
4 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16, SSOP16, TSSOP16 and
DHVQFN16 packages
[1]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
-
65
Max
+7
20
20
25
50
50
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
T
amb
=
40 C
to +125
C
[1]
-
-
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Conditions
Min
V
CC
V
I
V
O
t/V
supply voltage
input voltage
output voltage
input transition rise and
fall rate
except for
Schmitt trigger inputs
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
T
amb
ambient temperature
-
-
-
40
-
1.67
-
+25
625
139
83
+125
-
-
-
40
-
1.67
-
+25
-
139
-
+125
ns/V
ns/V
ns/V
C
2.0
0
0
74HC4020
Typ
5.0
-
-
Max
6.0
V
CC
V
CC
Min
4.5
0
0
74HCT4020
Typ
5.0
-
-
Max
5.5
V
CC
V
CC
V
V
V
Unit
Symbol Parameter
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
5 of 20
Power technology
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