BUK963R1-40E
13 July 2012
N-channel TrenchMOS logic level FET
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel MOSFET in a SOT404 package using TrenchMOS technology.
This product has been designed and qualified to AEC Q101 standard for use in high
performance automotive applications.
1.2 Features and benefits
•
AEC Q101 compliant
•
Repetitive avalanche rated
•
Suitable for thermally demanding environments due to 175 °C rating
•
True logic level gate with Vgst(th) rating of greater than 0.5V at 175 °C
1.3 Applications
•
12 V Automotive systems
•
Motors, lamps and solenoid control
•
Start-Stop micro-hybrid applications
•
Transmission control
•
Ultra high performance power switching
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 1
T
mb
= 25 °C;
Fig. 2
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
[1]
Min
-
-
-
Typ
-
-
-
Max
40
100
234
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
gate-drain charge
-
2.6
3.1
mΩ
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 25 A; V
DS
= 32 V;
Fig. 13; Fig. 14
[1]
Continuous current is limited by package.
-
25.8
-
nC
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NXP Semiconductors
BUK963R1-40E
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to
drain
2
1
3
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
D2PAK (SOT404)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK963R1-40E
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ
T
j
= 25 °C
T
j
= 25 °C; lifetime = 100 hours
I
D
drain current
T
mb
= 25 °C; V
GS
= 5 V;
Fig. 1
T
mb
= 100 °C; V
GS
= 5 V;
Fig. 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
peak drain current
total power dissipation
storage temperature
junction temperature
T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 4
T
mb
= 25 °C;
Fig. 2
[1]
[1]
Min
-
-
-10
-15
-
-
-
-
-55
-55
Max
40
40
10
15
100
100
794
234
175
175
Unit
V
V
V
V
A
A
A
W
°C
°C
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
[1]
-
-
100
794
A
A
BUK963R1-40E
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© NXP B.V. 2012. All rights reserved
Product data sheet
13 July 2012
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NXP Semiconductors
BUK963R1-40E
N-channel TrenchMOS logic level FET
Symbol
E
DS(AL)S
Parameter
non-repetitive drain-source
avalanche energy
Conditions
I
D
= 100 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
Fig. 3
[2][3]
Min
-
Max
419
Unit
mJ
Avalanche ruggedness
[1]
[2]
[3]
200
I
D
(A)
150
Continuous current is limited by package.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
003aah315
120
P
der
(%)
80
03aa16
100
(1)
40
50
0
0
50
100
150
T
mb
(° C)
200
0
0
50
100
150
T
mb
(°C)
200
(1) Capped at 100A due to package
Fig. 1.
Continuous drain current as a function of
mounting base temperature
Fig. 2.
Normalized total power dissipation as a
function of mounting base temperature
10
3
I
AL
(A)
10
2
003aah316
(1)
10
(2)
1
(3)
10
-1
10
-3
10
-2
10
-1
1 t (ms) 10
AL
Fig. 3.
Single pulse avalanche rating; avalanche current as a function of avalanche time
BUK963R1-40E
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© NXP B.V. 2012. All rights reserved
Product data sheet
13 July 2012
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NXP Semiconductors
BUK963R1-40E
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
003aah317
t
p
=10 µ s
100 µ s
10
DC
1 ms
10 ms
1
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
1
Z
th(j-mb)
δ = 0.5
(K/W)
0.2
10
-1
Conditions
Fig. 5
Min
-
Typ
-
Max
0.64
Unit
K/W
R
th(j-a)
minimum footprint ; mounted on a
printed-circuit board
-
50
-
K/W
003aah318
0.1
0.05
0.02
10
-2
single shot
P
δ=
t
p
T
t
p
t
T
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK963R1-40E
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© NXP B.V. 2012. All rights reserved
Product data sheet
13 July 2012
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NXP Semiconductors
BUK963R1-40E
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 9; Fig. 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 9
I
DSS
drain leakage current
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 40 V; V
GS
= 0 V; T
j
= 175 °C
I
GSS
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 5 V; I
D
= 25 A; T
j
= 175 °C;
Fig. 12; Fig. 11
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain
inductance
internal source
inductance
from upper edge of drain mounting
base to center of die
from source lead to source bonding
pad
All information provided in this document is subject to legal disclaimers.
Min
40
36
1.4
-
0.5
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
0.06
-
2
2
2.6
2.25
-
Max
-
-
2.1
2.45
-
1
500
100
100
3.1
2.7
6
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
V
GS(th)
I
D
= 25 A; V
DS
= 32 V; V
GS
= 5 V;
Fig. 13; Fig. 14
-
-
-
69.5
16.1
25.8
6870
875
450
42
73
114
76
2.5
7.5
-
-
-
9150
1050
620
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
T
j
= 25 °C;
Fig. 15
-
-
-
V
DS
= 30 V; R
L
= 1.2 Ω; V
GS
= 5 V;
R
G(ext)
= 5 Ω
-
-
-
-
-
-
BUK963R1-40E
© NXP B.V. 2012. All rights reserved
Product data sheet
13 July 2012
5 / 12