IDT71V3577S80PFGI datasheet, PDF

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IDT71V3577S80PFGI: DescriptionCache SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100; Categorystorage storage; File Size519KB，22 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT71V3577S80PFGI Overview

Cache SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

IDT71V3577S80PFGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	8 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

IDT71V3577S80PFGI Preview

128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Features

IDT71V3577S

IDT71V3579S

IDT71V3577SA

IDT71V3579SA

Description

The IDT71V3577/79 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to gen-

erate a self-timed write based upon a decision which can be left until the

end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V3577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5280 tbl 01

128K x 36, 256K x 18 memory configurations

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW byte write

GW),

enable (BWE and byte writes (BW

BWE),

BWx)

BWE

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Pin Description Summary

-A

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

NOTE:

and

are not applicable for the IDT71V3579.

FEBRUARY 2005

DSC-5280/08

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

Symbol

-A

Pin Function

Address Inputs

Address Status

(Cache Controller)

Address Status

(Processor)

Burst Address

Advance

Byte Write Enable

I/O

Active

N/A

LOW

Description

Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK

and

ADSC

Low or

ADSP

Low and

Low.

Synchronous Addre ss Status from Cache Controller.

ADSC

is an active LOW input that is used to load the

address registers with new addresses.

Synchronous Address Status from Processor.

ADSP

is an active LOW input that is used to load the address

registers with new addresses.

ADSP

is gated by

Synchronous Address Advance.

ADV

is an active LOW input that is used to advance the internal burst counter,

controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not

incremented; that is, there is no address advance.

Synchronous byte write enable gates the byte write inputs

. If

BWE

is LOW at the rising edge of CLK

then

x inputs are passed to the next stage in the circuit. If

BWE

is HIGH then the byte write inputs are

blocked and only

can initiate a write cycle.

Synchronous byte write enables.

controls I/O

0-7

, I/O

controls I/O

8-15

, I/O

, etc. Any active byte

write causes all outputs to be disabled.

Synchronous chip enable.

is used with CS

and

to enable the IDT71V3577/79.

also gates

ADSP

This is the clock input. All timing references for the device are made with respect to this input.

Synchronous active HIGH chip select. CS

is used with

and

to enable the chip.

Synchronous active LOW chip select.

is used with

and CS

to enable the chip.

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of

CLK.

supersedes individual byte write enables.

Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of

CLK. The data o utput path is flow-through (no output register).

Asynchronous b urst order selection input. When

LBO

is HIGH, the inter-leaved burst sequence is selected.

When

LBO

is LOW the Linear burst sequence is selected.

LBO

is a static input and must not change state

while the device is operating.

Asynchronous output enable. When

is LOW the data output drivers are enabled on the I/O pins if the chip

is also selected. When

is HIGH the I/O pins are in a high-impedance state.

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an

internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the

TAP controller.

Optional Asynchronous JTAG rese t. Can be used to reset the TAP contro ller, but not required. JTAG reset

occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used

TRST

can

be left floating. This pin has an internal pullup. Only available in BGA package.

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3577/79 to

its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull

down.

3.3V core power supply.

3.3V I/O Supply.

Ground.

NC pins are not electrically connected to the device.

5280 tbl 02

ADSC

ADSP

ADV

BWE

LOW

CLK

Individual Byte

Write Enables

Chip Enable

Clock

Chip Select 0

Chip Select 1

Global Write

Enable

Data Input/Output

Linear Burst Order

I/O

LOW

N/A

HIGH

LOW

N/A

LOW

I/O

-I/O

I/O

-I/O

LBO

TMS

TDI

TCK

TDO

Output Enable

Test ModeSelect

Test Data Input

Test Clock

Test DataOutput

JTAG Reset

(Optional)

LOW

N/A

TRST

LOW

DDQ

Sleep Mode

Power Supply

Ground

No Connect

N/A

HIGH

N/A

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

ADV

CEN

Burst

Sequence

INTERNAL

ADDRESS

CLK

ADSC

ADSP

CLK EN

ADDRESS

Byte 1

Write Register

Binary

Counter

CLR

Burst

Logic

17/18

A0*

A1*

128K x 36/

256K x 18-

BIT

MEMORY

ARRAY

17/18

2 -

36/18

0 -

16/17

BWE

Byte 1

Write Driver

Byte 2

Write Register

Byte 2

Write Driver

Byte 3

Write Register

Byte 3

Write Driver

Byte 4

Write Register

Byte 4

Write Driver

Enable

DATA INPUT

CLK EN

Powerdown

I/O

- I/O

I/O

- I/O

36/18

OUTPUT

BUFFER

TMS

TDI

TCK

5280 drw 01

JTAG

(SA Version)

TDO

TRST

(Optional)

6.42

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Symbol

TERM

(2)

Rating

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Commercial

Operating Temperature

Industrial

Operating Temperature

Commercial &

Industrial Values

-0.5 to +4.6

-0.5 to V

+0.5

-0.5 to V

DDQ

+0.5

-0 to +70

-40 to +85

-55 to +125

2.0

Unit

Recommended Operating

Temperature Supply Voltage

Grade

Commercial

Industrial

Temperature

(1)

0°C to +70°C

-40°C to +85°C

3.3V± 5%

DDQ

3.3V± 5%

5280 tbl 04

TERM

(3,6)

TERM

(4,6)

TERM

(5,6)

NOTES:

1. T

is the "instant on" case temperature.

Recommended DC Operating

Conditions

Symbol

DDQ

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

Min.

3.135

2.0

-0.3

(2)

Typ.

3.3

____

(7)

Max.

3.465

+0.3

DDQ

+0.3

(1)

0.8

Unit

BIAS

STG

OUT

Temperature

Under Bias

Storage

Temperature

Power Dissipation

DC Output Current

5280 tbl 03

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V

terminals only.

3. V

DDQ

terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed V

DDQ

during power supply ramp up.

7. T

is the "instant on" case temperature.

5280 tbl 06

NOTES:

1. V

(max) = V

DDQ

+ 1.0V for pulse width less than t

CYC/2

, once per cycle.

2. V

(min) = -1.0V for pulse width less than t

CYC/2

, once per cycle.

100 Pin TQFP Capacitance

= +25° C, f = 1.0mhz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

5280 tbl 07

119 BGA Capacitance

= +25° C, f = 1.0mhz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

5280 tbl 07a

165 fBGA Capacitance

= +25° C, f = 1.0mhz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

5280 tb l 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36

CLK

BWE

ADSC

ADSP

ADV

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/O

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

I/O

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

I/O

DDQ

I/O

DDQ

I/O

(2)

I/O

DDQ

I/O

DDQ

I/O

5280 drw 02a

LBO

100 TQFP

Top View

NOTES:

1. Pin 14 does not have to be directly connected to V

as long as the input voltage is < V

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

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