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74LVX161284A Low Voltage IEEE 161284 Translating Transceiver
June 1999
Revised June 2005
74LVX161284A
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284A contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard, with the exception of output slew rate,
and is intended to be used in an Extended Capabilities Port
mode (ECP). The pinout allows for easy connection from
the Peripheral (A-side) to the Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
r
14 mA) and are connected to a
separate power supply pin (V
CC
cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the V
CC
cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A
1
–A
8
/B
1
–B
8
transceiver
pins.
Features
s
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
with the exception of output slew rate
s
Translation capability allows outputs on the cable side to
interface with 5V signals
s
All inputs have hysteresis to provide noise margin
s
B and Y output resistance optimized to drive external
cable
s
B and Y outputs in high impedance mode during power
down
s
Inputs and outputs on cable side have internal pull-up
resistors
s
Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
s
Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number
74LVX161284AMTD
74LVX161284AMTX
Package
Number
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Connection Diagram
Pin Descriptions
Pin Names
HD
DIR
A
1
–A
8
B
1
–B
8
A
9
–A
13
Y
9
–Y
13
A
14
–A
17
C
14
–C
17
PLH
IN
PLH
HLH
IN
HLH
Description
High Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
© 2005 Fairchild Semiconductor Corporation
DS500204
www.fairchildsemi.com
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