IDT70V5388S166BC8 datasheet, PDF

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IDT70V5388S166BC8: DescriptionFour-Port SRAM, 64KX18, 3.2ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, BGA-256; Categorystorage storage; File Size390KB，29 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70V5388S166BC8 Overview

Four-Port SRAM, 64KX18, 3.2ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, BGA-256

IDT70V5388S166BC8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	17 X 17 MM, 1 MM PITCH, BGA-256
Contacts	256
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	3.2 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	17 mm
memory density	1179648 bit
Memory IC Type	FOUR-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	4
Number of terminals	256
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum standby current	0.015 A
Minimum standby current	3.15 V
Maximum slew rate	0.395 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	17 mm

IDT70V5388S166BC8 Preview

3.3V 64/32K X 18

SYNCHRONOUS

FOURPORT™ STATIC RAM

Features

◆

IDT70V5388/78

◆

True four-ported memory cells which allow simultaneous

access of the same memory location

Synchronous Pipelined device

– 64/32K x 18 organization

Pipelined output mode allows fast 200MHz operation

High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x

4 ports)

LVTTL I/O interface

High-speed clock to data access 3.0ns (max.)

3.3V Low operating power

Interrupt flags for message passing

Width and depth expansion capabilities

◆

Counter wrap-around control

– Internal mask register controls counter wrap-around

– Counter-Interrupt flags to indicate wrap-around

Counter readback on address lines

Mask register readback on address lines

Global Master reset for all ports

Dual Chip Enables on all ports for easy depth expansion

Separate upper-word and lower-word controls on all ports

272-BGA package (27mm x 27mm 1.27mm ball pitch) and

256-BGA package (17mm x 17mm 1.0mm ball pitch)

Commercial and Industrial temperature ranges

JTAG boundary scan

MBIST (Memory Built-In Self Test) controller

Port - 1 Logic Block Diagram

(2)

0P1

1P1

1 /0

I/O

9P1

- I/O

17P1

I/O

0P1

- I/O

8P1

Port 1

I/O

Control

TRST

TMS

TCK

TDI

CLKMBIST

JTAG

Controller

MBIST

TDO

Addr.

Read

Back

Port 1

Readback

MRST

0P1

- A

15P1

(1)

CNTRD

MKRD

MKLD

CNTINC

CNTLD

CNTRST

CLK

MRST

CNTINT

Port 1

Mask

Priority

Decision

Logic

Port 1

Counter/

Address

Port 1

Address

Decode

64KX18

Memory

Array

0P1

1P1

CLK

Port 1

Interrupt

Logic

INT

MRST

NOTE:

1. A

x is a NC for IDT70V5378.

2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.

5649 drw 01

AUGUST 2003

DSC-5649/3

IDT70V5388/78

3.3V 64/32K x 18 Synchronous FourPort™ Static RAM

Industrial and Commercial Temperature Ranges

The IDT70V5388/78 is a high-speed 64/32Kx18 bit

synchronous FourPort RAM. The memory array utilizes

FourPort memory cells to allow simultaneous access of

any address from all four ports. Registers on control, data,

and address inputs provide minimal setup and hold times.

The timing latitude provided by this approach allows sys-

tems to be designed with very short cycle times.

With an input data register and integrated burst

counters, the 70V5388/78 has been optimized for applica-

tions having unidirectional or bi-directional data flow in

bursts. An automatic power down feature, controlled by

and CE

, permits the on-chip circuitry of each port to enter

a very low standby power mode.

The IDT70V5388/78 provides a wide range of func-

Description

tions specially designed to facilitate system operations.

These include full-boundary, maskable address counters

with associated interrupts for each port, mailbox interrupt

flags on each port to facilitate inter-port communications,

Memory Built-In Self-Test (MBIST), JTAG support and an

asynchronous Master Reset to simplify device initializa-

tion. In addition, the address lines have been set up as I/O

pins, to permit the support of

CNTRD

(the ability to output the

current value of the internal address counter on the address

lines) and

MKRD

(the ability to output the current value of the

counter mask register). For specific details on the device

operation, please refer to the Functional Description and

subsequent explanatory sections, beginning on page 21.

IDT70V5388/78

3.3V 64/32K x 18 Synchronous FourPort™ Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(4)

70V5388/78BG

BG-272

(2)

272-Pin BGA

Top View

(3)

09/25/02

I/O

(1)

INT

(1)

I/O

R/W

I/O

10 11 12

I/O

TMS

I/O

TDI

I/O

13 14 15 16 17 18 19 20

I/O

R/W

I/O

(1)

TCK

TDO

MKRD CNTRD

CNTINT

CNTINC

CNTRD MKRD

CNTINT

CNTINC

MKLD CNTLD

CNTRST

CNTLD MKLD

GND

(5)

CLK

GND

(5)

GND

(5)

GND

(5)

GND

(5)

GND

(5)

GND

(5)

GND

(5)

CLK

CNTRST

INT

CLK

CNTRST

INT

CNTRST

GND

(5)

GND

(5)

GND

(5)

GND

(5)

CLK

GND

(5)

GND

(5)

GND

(5)

GND

(5)

(1)

I/O

MKLD CNTLD

CNTINC

CNTINT

CNTLD MKLD

CNTINC

CNTINT

MKRD CNTRD

I/O

R/W

I/O

R/W

I/O

CNTRD MKRD

I/O

TRST

I/O

MRST

CLKMBIST

I/O

10 11 12

13 14 15 16 17 18 19 20

5649 drw 03

NOTES:

1. A

x is a NC for IDT70V5378.

2. This package code is used to reference the package diagram.

3. This text does not indicate orientation of the actual part marking.

4. Package body is approximately 27mm x 27mm x 2.33mm, with 1.27mm ball-pitch.

5. Central balls are for thermal dissipation only. They are connected to device V

6.42

IDT70V5388/78

3.3V 64/32K x 18 Synchronous FourPort™ Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(2)

70V5388/78BC

BC-256

(3)

256-Pin BGA

(4)

Top View

09/25/02

R/W

I/O

12 13 14

I/O

15 16

I/O

(1)

I/O

TDI

TDO

TCK

I/O

R/W

I/O

(1)

I/O

TMS

I/O

INT

CLK

CNTRD

CNTINC

CNTLD

CNTINC

CNTRD

CLK

CNTLD

CNTRST CNTINT

MKLD

CNTRST

MKRD

INT

CNTINT

MKLD

CLK

CNTRST

INT

CNTINT

MKRD

I/O

CNTRST

INT

CNTINT

MKLD

CNTRD

MKRD

CNTINC

CNTLD MKLD

CNTLD

CNTINC

MKRD

CNTRD

I/O

TRST

MRST

CLKMBIST

I/O

R/W

I/O

(1)

I/O

(1)

I/O

R/W

10 11

12 13 14 15 16

5649 drw 04

NOTES:

1. A

x is a NC for IDT70V5378.

2. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

3. This package code is used to reference the package diagram.

4. This text does not indicate orientation of the actual part-marking.

IDT70V5388/78

3.3V 64/32K x 18 Synchronous FourPort™ Static RAM

Industrial and Commercial Temperature Ranges

Pin Definitions

Port 1

0P1

- A

15P1

(1)

I/O

0P1

- I/O

17P1

CLK

Port 2

0P2

- A

15P2

(1)

I/O

0P2

- I/O

17P2

CLK

Port 3

0P3

- A

15P3

(1)

I/O

0P3

- I/0

17P3

CLK

Port 4

0P4

- A

15P4

(1)

I/O

0P4

- I/O

17P4

CLK

Description

Address Inputs. In the

CNTRD

and

MKRD

operations, these pins serve

as outputs for the internal address counter and the internal counter mask

Data Bus Input/Output.

Clock Input. The maximum clock input rate is f

MAX

. The clock signal can

be free running or strobed depending on system requirements.

Master Reset Input.

MRST

is an asycnchronous input, and affects all

ports. It must be asserted LOW (MRST = V

) at initial power-up. Master

Reset sets the internal value of all address counters to zero, and sets

the counter mask registers for each port to 'unmasked'. It also resets the

output flags for the mailboxes and the counter interrupts (INT =

CNTINT

= V

) and deselects all registered control signals.

0P2

, CE

1P2

0P3

, CE

1P3

0P4

, CE

1P4

Chip Enable Inputs. To activate any port, both signals must be asserted

to their active states

(CE

= V

, CE

= V

). A given port is disabled if

either chip enable is deasserted (CE

= V

and/or CE

= V

Read/Write Enable Input. This signal is asserted LOW (R/

= V

) in

order to write to the FourPort memory array, and it is asserted HIGH

(R/W = V

) in order to read from the array.

Lower Byte Select Input (I/O

- I/O

). Asserting this signal LOW (LB = V

)

enables read/write operations to the lower byte. For read operations, this

signal is used in conjunction with

in order to drive output data on the

lower byte of the data bus.

Upper Byte Select Input (I/O

- I/O

). Asserting this signal LOW (LB =

) enables read/write operations to the upper byte. For read

operations, this signal is used in conjunction with

in order to drive

output data on the upper byte of the data bus.

Output Enable Input. Asserting this signal LOW (OE = V

) enables the

device to drive data on the I/O pins during read operation.

is an

asychronous input.

Counter Load Input. Asserting this signal LOW (CNTLD = V

) loads the

address on the address lines (A

- A

(1)

) into the internal address

counter for that port.

Counter Increment Input. Asserting this signal LOW (CNTINC = V

)

increments the internal address counter for that port on each rising edge

of the clock signal. The counter will increment as defined by the counter

mask register for that port (default mode is to advance one address on

each clock cycle).

Counter Readback Input. When asserted LOW (CNTRD = V

) causes that

port to output the value of its internal address counter on the address

lines for that port. Counter readback is independent of the chip enables

for that port. If the port is activated (CE

= V

and CE

= V

), during the

counter readback operation, then the data bus will output the data

associated with that readback address in the FourPort memory array

(assuming that the byte enables and output enables are also asserted).

Truth Table III indicates the required states for all other counter controls

during this operation. The specific operation and timing of this funcion is

described in detail in the text.

Counter Reset Input. Asserting this signal LOW

(CNTRST

= V

) resets

the address counter for that port to zero.

Counter Interrupt Flag Output. This signal is asserted LOW (CNTINT =

) when the internal address counter for that port 'wraps around' from

max address [(the counter will increment as defined by the counter mask

clock cycle)] to address min. as the result of counter increment (CNTINT

= V

). The signal goes LOW for one clock cycle, then automatically

resets.

5649 tbl 01

MRST

0P1

, CE

1P1

R/W

CNTLD

CNTINC

CNTRD

CNTRST

CNTINT

6.42

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