IS61VF204818A-7.5B3I datasheet, PDF

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IS61VF204818A-7.5B3I: DescriptionCache SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165; Categorystorage storage; File Size386KB，20 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61VF204818A-7.5B3I Overview

Cache SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165

IS61VF204818A-7.5B3I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	13 X 15 MM, PLASTIC, BGA-165
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	117 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	37748736 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.145 A
Minimum standby current	2.38 V
Maximum slew rate	0.35 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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IS61LF102436A IS61VF102436A

IS61LF204818A IS61VF204818A

1M x 36, 2M x 18

36Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• Power Supply

LF: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VF: V

2.5V + 5%,

ddq

2.5V + 5%

• JEDEC 100-Pin TQFP and 165-pin PBGA pack-

ages.

• Lead-free available

APRIL 2008

DESCRIPTION

The

ISSI

IS61LF/VF102436A and IS61LF/VF204818A

are high-speed, low-power synchronous static RAMs de-

signed to provide burstable, high-performance memory for

communication and networking applications. The IS61LF/

VF102436A is organized as 1,048,476 words by 36 bits.

The IS61LF/VF204818A is organized as 2M-words by 18

bits. Fabricated with

ISSI

's advanced CMOS technology,

the device integrates a 2-bit burst counter, high-speed

SRAM core, and high-drive capability outputs into a single

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write en-

able (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-6.5

6.5

7.5

133

-7.5

7.5

8.5

117

Units

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. B

04/17/08

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