M28010
1 Mbit (128K x 8) Parallel EEPROM
With Software Data Protection
DATA BRIEFING
s
s
Fast Access Time: 100 ns
Single Supply Voltage:
– 4.5 V to 5.5 V for M28010
– 2.7 V to 3.6 V for M28010-W
– 1.8 V to 2.4 V for M28010-R
32
s
s
s
Low Power Consumption
Fast BYTE and PAGE WRITE (up to 128 Bytes)
Enhanced Write Detection and Monitoring:
– Data Polling
– Toggle Bit
– Page Load Timer Status
PDIP32 (BA)
1
s
s
s
s
s
s
JEDEC Approved Bytewide Pin-Out
Software Data Protection
Hardware Data Protection
Software Chip Erase
100000 Erase/Write Cycles (minimum)
Data Retention (minimum): 10 Years
PLCC32 (KA)
TSOP32 (NA)
8 x 20 mm
DESCRIPTION
The M28010 devices consist of 128Kx8 bits of low
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary double polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a sin-
gle voltage supply (5V, 3V or 2V, depending on the
option chosen).
Figure 1. Logic Diagram
VCC
17
A0-A16
8
DQ0-DQ7
Table 1. Signal Names
A0-A16
DQ0-DQ7
W
E
G
V
CC
V
SS
Address Input
Data Input / Output
Write Enable
W
E
G
M28010
Chip Enable
Output Enable
Supply Voltage
Ground
VSS
AI02221
January 1999
Complete data available on
Data-on-Disc CD-ROM
or at
www.st.com
1/3
M28010
Figure 2A. DIP Connections
DU
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
32
1
31
2
30
3
29
4
28
5
27
6
26
7
8
M28010 25
24
9
23
10
22
11
21
12
20
13
19
14
18
15
17
16
AI02222
Figure 2C. TSOP Connections
VCC
W
DU
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
A14
DU
W
VCC
DU
A16
A15
A12
A7
A6
A5
A4
1
32
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
8
9
M28010
25
24
16
17
AI02224
Note: 1. DU = Do Not Use
Note: 1. DU = Do Not Use
Figure 2B. PLCC Connections
A12
A15
A16
DU
VCC
W
DU
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M28010
25
data retention. The organization of the data in a 4
byte (32-bit) “word” format leads to significant sav-
ings in power consumption. Once a byte has been
read, subsequent byte read cycles from the same
“word” (with addresses differing only in the two
least significant bits) are fetched from the previ-
ously loaded Read Buffer, not from the memory ar-
ray. As a result, the power consumption for these
subsequent read cycles is much lower than the
power consumption for the first cycle. By careful
design of the memory access patterns, a 50% re-
duction in the power consumption is possible.
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
AI02223
Note: 1. DU = Do Not Use
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 2. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
The device has been designed to offer a flexible
microcontroller interface, featuring both hardware
and software hand-shaking, with Data Polling and
Toggle Bit. The device supports a 128 byte Page
Write operation. Software Data Protection (SDP)
is also supported, using the standard JEDEC algo-
rithm.
The M28010 is designed for applications requiring
as much as 100,000 write cycles and ten years of
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