W78C58
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C58 is a derivative of the W78C52 microcontroller family that provides extended internal
ROM. The chip has 32K bytes of mask ROM and 256 bytes of RAM.
This device provides an enhanced architecture that makes it more powerful and suitable for a variety
of applications for general control systems. It provides on-chip 32KB mask ROM to accommodate
large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port,
three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator
clock circuits.
FEATURES
•
DC to 40 MHz extensive operating frequency
•
256-byte on-chip scratch pad RAM
•
32K-byte on-chip mask ROM
•
64K-byte address space for external Program Memory
•
64K-byte address space for external Data Memory
•
Three 16-bit timer/counters
•
Four 8-bit bit-addressable I/O ports
•
One extra 4-bit bit-addressable I/O port, additonal
INT2
/ INT3
(Available on 44-pin PLCC/QFP package)
•
Eight-source, two priority-level interrupts
•
Low EMI emission mode
•
Built-in programmable power-saving modes - Idle mode & Power-down mode
•
Packages:
−
DIP 40: W78C58-16/24/40
−
PLCC 44: W78C58P-16/24/40
−
QFP 44: W78C58F-16/24/40
−
TQFP 44: W78C58M-16/24/40
-1-
Publication Release Date: December 1997
Revision A5
W78C58
PIN CONFIGURATIONS
40-Pin DIP (W78C58)
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin PLCC (W78C58P)
/
I
N
T
3
,
P
4 V
. C
2 C
44-Pin QFP/TQFP (W78C58F/W78C58M)
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
/
I
N
T T
2 3
, ,
P P
1 4 V
. . C
0 2 C
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
T
2
,
P
1
.
0
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P1.5
P1.6
P1.7
RST
RXD, P3.
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P
T S 4
A S .
L
0
1
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
44 43 42 41 40 39 38 37 36 35 34
1
33
32
2
31
3
30
4
29
5
28
6
27
7
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-2-
W78C58
PIN DESCRIPTION
SYMBOL
EA
TYPE
I
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out
of external ROM. The ROM address and data will not be present on the bus if
the
EA
pin is high and the program counter is within the 32 KB area.
Otherwise they will be present on the bus.
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus.
When internal ROM access is performed, no PSEN strobe signal outputs
originate from this pin.
ALE
O H
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential.
POWER SUPPLY: Supply voltage for operation.
PORT 0: Function is the same as that of the standard 8052.
PORT 1: Function is the same as that of the standard 8052.
PORT 2: Function is the same as that of the standard 8052.
PORT 3: Function is the same as that of the standard 8052.
PORT 4: A 4-bit bi-directional parallel port and bit-addressable with internal
pull-ups. Pin P4.3 and P4.2 have alternative function as external interrupt
(INT2/INT3) source input.
External interrupt 2: An extra interrupt input source. It cascades to pin P4.3
internally.
External interrupt 3: An extra interrupt input source. It cascades to pin P4.2
internally.
PSEN
O H
RST
XTAL1
XTAL2
V
SS
V
DD
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
P3.0−P3.7
P4.0−P4.3
I L
I
O
I
I
I/O D
I/O H
I/O H
I/O H
I/O H
INT2 (P4.3)
INT3 (P4.2)
I H
I H
* Note :
TYPE
I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
-3-
Publication Release Date: December 1997
Revision A5
W78C58
BLOCK DIAGRAM
P1.0
~
P1.7
Port
1
Port 1
Latch
ACC
B
Port 0
Latch
Port
0
INT2
Interrupt
INT3
T1
Timer
2
Timer
0
Timer
1
UART
PSW
ALU
T2
P0.0
~
P0.7
DPTR
Stack
Pointer
Temp Reg.
PC
Incrementor
Addr. Reg.
P3.0
~
P3.7
Port
3
Port 3
Latch
Instruction
Decoder
&
Sequencer
SFR RAM
Address
32KB
ROM
256 bytes
RAM & SFR
Port
2
Bus & Clock
Controller
Port 2
Latch
P2.0
~
P2.7
P4.0
~
P4.3
Port
4
Port 4
Latch
Oscillator
Reset Block
Power control
XTAL1 XTAL2 ALE PSEN
RST
VCC
GND
Figure 2. Architecture of the W78C58
-4-
W78C58
FUNCTIONAL DESCRIPTION
The W78C58 is pin-to-pin compatible with the W78C52, except that the internal 8K mask ROM has
been replaced with 32K of internal mask ROM. The processor supports 111 different opcodes and
references both 64K program address space and 64 K data storage space.
Clock
The W78C58 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78C58 relatively insensitive to duty cycle
variations in the clock.
Crystal Oscillator
The W78C58 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal is
connected across pins XTAL1 and XTAL2. In addition, a load capacitance of 30 pf (typically) must be
connected from each pin to ground. Resistor must also be connected from XTAL1 to XTAL2 to
provide a DC bias when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDLE bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the
W78C58
is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
-5-
Publication Release Date: December 1997
Revision A5
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