Preliminary W77E58
8 BIT MICROCONTROLLER
Table of Contents--
GENERAL DESCRIPTION ..............................................................................................................................2
FEATURES......................................................................................................................................................2
PIN CONFIGURATION ....................................................................................................................................3
PIN DESCRIPTION..........................................................................................................................................4
BLOCK DIAGRAM ...........................................................................................................................................6
FUNCTIONAL DESCRIPTION ........................................................................................................................7
MEMORY ORGANIZATION.............................................................................................................................8
INSTRUCTION...........................................................................................................................................29
INSTRUCTION TIMING .............................................................................................................................37
POWER MANAGEMENT ..........................................................................................................................46
RESET CONDITIONS................................................................................................................................48
RESET STATE...........................................................................................................................................49
PROGRAMMABLE TIMERS/COUNTERS ....................................................................................................53
TIMED ACCESS PROTECTION ...................................................................................................................70
ON-CHIP MTP ROM CHARACTERISTICS...................................................................................................71
SECURITY BITS ............................................................................................................................................74
ABSOLUTE MAXIMUM RATINGS ................................................................................................................75
DC ELECTRICAL CHARACTERISTICS ......................................................................................................76
AC ELECTRICAL CHARACTERISTICS........................................................................................................77
TYPICAL APPLICATION CIRCUITS .............................................................................................................82
Expanded External Program Memory and Crystal......................................................................................82
Expanded External Data Memory and Oscillator ........................................................................................83
PACKAGE DIMENSIONS..............................................................................................................................83
40-pin DIP...................................................................................................................................................83
44-pin PLCC ...............................................................................................................................................84
44-pin QFP .................................................................................................................................................84
-1-
Publication Release Date: March 1999
Revision A1
Preliminary W77E58
GENERAL DESCRIPTION
The W77E58 is a fast 8051 compatible microcontroller with a redesigned processor core without
wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the
original 8051 for the same crystal speed. Typically, the instruction executing time of W77E58 is 1.5 to
3 times faster then that of traditional 8051, depending on the type of instruction. In general, the
overall performance is about 2.5 times better than the original for the same crystal speed. Giving the
same throughput with lower clock speed, power consumption has been improved. Consequently, the
W77E58 is a fully static CMOS design; it can also be operated at a lower crystal clock. The W77E58
contains 32 KB flash Multiple-Time Programmable(MTP) ROM, and provides operating voltage from
4.5V to 5.5V. All W77E58 types also support on-chip 1 KB SRAM without external memory
component and glue logic, saving more I/O pins for users
’
application usage if they use on-chip
SRAM instead of external SRAM.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit CMOS microcontroller
High speed architecture of 4 clocks/machine cycle runs up to 40 MHz
Pin compatible with standard 80C52
Instruction-set compatible with MCS-51
Four 8-bit I/O Ports
One extra 4-bit I/O port and Wait State control signal (available on 44-pin PLCC/QFP package)
Three 16-bit Timers
12 interrupt sources with two levels of priority
On-chip oscillator and clock circuitry
Two enhanced full duplex serial ports
32 KB flash Multiple-Time Programmable(MTP) ROM
256 bytes scratch-pad RAM
1 KB on-chip SRAM for MOVX instruction
Programmable Watchdog Timer
Dual 16-bit Data Pointers
Software programmable access cycle to external RAM/peripherals
Packages:
−
DIP 40: W77E58-25/40
−
PLCC 44: W77E58P-25/40
−
QFP 44: W77E58F-25/40
-2-
Preliminary W77E58
PIN CONFIGURATION
40-Pin DIP (W77E58)
T2, P1.0
T2EX, P1.1
RXD1, P1.2
TXD1, P1.3
INT2, P1.4
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin PLCC (W77E58P)
44-Pin QFP (W77E58F)
I
N
T
2
,
P
1
.
4
T
X
D
1
,
P
1
.
3
R
X
D
1
,
P
1
.
2
T
2
E
X
,
P
1
.
1
I
N
T
2
,
P
1
.
4
T
X
D
1
,
P
1
.
3
R
X
D
1
,
P
1
.
2
T
2
E
X
,
P
1
.
1
T
2
,
P
1
.
0
P
4 V
. D
2 D
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
T
2
,
P
1
.
0
P
4 V
. D
2 D
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P
T S 4
A S .
0
L
,
1
/
W
A
I
T
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
1
2
3
4
5
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
6
27
7
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P
T S 4
A S .
0
L
,
1
/
W
A
I
T
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-3-
Publication Release Date: March 1999
Revision A1
Preliminary W77E58
PIN DESCRIPTION
SYMBOL
EA
TYPE
I
DESCRIPTIONS
EXTERNAL ACCESS ENABLE:
This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM
address and data will not be present on the bus if
EA
pin is high and the
program counter is within 32 KB area. Otherwise they will be present on the
bus.
PROGRAM STORE ENABLE:
PSEN enables the external ROM data onto the
Port 0 address/data bus during fetch and MOVC operations. When internal
ROM access is performed, no PSEN strobe signal outputs from this pin.
ADDRESS LATCH ENABLE:
ALE is used to enable the address latch that
separates the address from the data on Port 0.
RESET:
A high on this pin for two machine cycles while the oscillator is running
resets the device.
CRYSTAL1:
This is the crystal oscillator input. This pin may be driven by an
external clock.
CRYSTAL2:
This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND:
Ground potential
POWER SUPPLY:
Supply voltage for operation.
PORT 0:
Port 0 is an open-drain bi-directional I/O port. This port also provides
a multiplexed low order address/data bus during accesses to external memory.
PORT 1:
Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
RXD1(P1.2): Serial port 2 RXD
TXD1(P1.3): Serial port 2 TXD
INT2(P1.4): External Interrupt 2
INT3 (P1.5): External Interrupt 3
INT4(P1.6): External Interrupt 4
INT5 (P1.7): External Interrupt 5
PSEN
O
ALE
RST
XTAL1
XTAL2
V
SS
V
DD
P0.0−P0.7
P1.0−P1.7
O
I
I
O
I
I
I/O
I/O
P2.0−P2.7
I/O
PORT 2:
Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
-4-
Preliminary W77E58
Pin Description, continued
SYMBOL
P3.0−P3.7
TYPE
I/O
DESCRIPTIONS
PORT 3:
Port 3 is a bi-directional I/O port with internal pull-ups. All bits have
alternate functions, which are described below:
RXD(P3.0) : Serial Port 0 input
TXD(P3.1) : Serial Port 0 output
INT0 (P3.2) : External Interrupt 0
INT1
(P3.3) : External Interrupt 1
T0(P3.4)
T1(P3.5)
: Timer 0 External Input
: Timer 1 External Input
WR
(P3.6) : External Data Memory Write Strobe
RD
(P3.7) : External Data Memory Read Strobe
P4.0−P4.3
I/O
PORT 4:
Port 4 is a 4-bit bi-directional I/O port. The P4.0 also provides the
alternate function
WAIT
which is the wait state control signal.
* Note:
TYPE
I: input, O: output, I/O: bi-directional.
-5-
Publication Release Date: March 1999
Revision A1
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