M29F002T, M29F002NT
M29F002B
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
NOT FOR NEW DESIGN
M29F002T, M29F002NT and M29F002B are
replaced respectively by the M29F002BT,
M29F002BNT and M29F002BB.
5V
±
10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29F002T: B0h
– Device Code, M29F002NT: B0h
– Device Code, M29F002B: 34h
DESCRIPTION
The M29F002 is a non-volatile memory that may be
erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 5V V
CC
supply. For Program and
Erase operations the necessary high voltages are
generated internally. The device can also be pro-
grammed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
July 2000
This is information on a product still in production but not recommended for new design.
32
1
PDIP32 (P)
PLCC32 (K)
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
VCC
18
A0-A17
W
E
G
(*) RPNC
M29F002T
M29F002B
M29F002NT
8
DQ0-DQ7
VSS
AI02078C
Note:
* RPNC function is not available for the M29F002NT
1/29
M29F002T, M29F002NT, M29F002B
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
(*) RPNC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
AI02080C
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
AI02079C
32
1
31
2
30
3
29
4
28
5
27
6
26
7
M29F002T 25
8
M29F002B
9 M29F002NT24
23
10
22
11
21
12
20
13
19
14
18
15
17
16
VCC
W
A17
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A12
A15
A16
RPNC
VCC
W
A17
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M29F002T
M29F002B
25
17
Note:
Pin 1 is not connected for the M29F002NT
Figure 2C. TSOP Pin Connections
Table 1. Signal Names
A0-A17
DQ0-DQ7
Address Inputs
Data Input/Outputs, Command Inputs
Chip Enable
Output Enable
Write Enable
Reset / Block Temporary Unprotect
Supply Voltage
Ground
A11
A9
A8
A13
A14
A17
W
VCC
RPNC
A16
A15
A12
A7
A6
A5
A4
1
32
8
9
M29F002T
M29F002B
25
24
16
17
AI02361B
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
E
G
W
RPNC
(*)
V
CC
V
SS
DESCRIPTION
(cont’d)
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for reading
the Electronic Signature or Block Protection status,
Programming, Block and Chip Erase, Erase Sus-
pend and Resume are written to the device in
cycles of commands to a Command Interface using
standard microprocessor write timings. The device
is offered in PLCC32, PDIP32 and TSOP32 (8 x 20
mm) packages.
2/29
M29F002T, M29F002NT, M29F002B
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
(A9, E, G, RPNC)
(2)
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9, E, G, RPNC Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–0.6 to 7
–0.6 to 7
–0.6 to 13.5
Unit
°C
°C
°C
V
V
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
Organisation
The M29F002 is organised as 256K x 8. Memory
control is provided by Chip Enable E, Output Enable
G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RPNC
(NOT available on M29F002NT) tri-level input pro-
vides a hardware reset when pulled Low, and when
held High (at V
ID
) temporarily unprotects blocks
previously protected allowing them to be progra-
med and erased. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on DQ7
provides a Data Polling signal, and DQ6 and DQ2
provide Toggle signals to indicate the state of the
P/E.C operations.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. The
M29F002 has an array of 7 blocks, one Boot Block
of 16 KBytes, two Parameter Blocks of 8 KBytes,
one Main Block of 32 KBytes and three Main Blocks
of 64 KBytes.
The memory map is shown in Figure 3. Each block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managed automatically by the P/E.C. The block
erase operation can be suspended in order to read
from or program to any block not being ersased,
and then resumed. Block protection provides addi-
tional data security. Each block can be separately
protected or unprotected against Program or Erase
on programming equipment. All previously pro-
tected blocks can be temporarily unprotected in the
application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
t e ct io n, Un pro te cti on, Prot ect ion Ver if y,
Unprotection Verify and Block Temporary Unprotec-
tion. See Tables 4 and 5.
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Command’
itself and its confirmation, when applicable, are
given on the third, fourth or sixth cycles. Any incor-
rect command or any improper command se-
quence will reset the device to Read Array mode.
3/29
M29F002T, M29F002NT, M29F002B
Figure 3. Memory Map and Block Address Table
M29F002T, M29F002NT
3FFFFh
16K BOOT BLOCK
3C000h
3BFFFh
8K PARAMETER BLOCK
3A000h
39FFFh
8K PARAMETER BLOCK
38000h
37FFFh
32K MAIN BLOCK
30000h
2FFFFh
64K MAIN BLOCK
20000h
1FFFFh
64K MAIN BLOCK
10000h
0FFFFh
64K MAIN BLOCK
00000h
00000h
AI02081C
M29F002B
3FFFFh
64K MAIN BLOCK
30000h
2FFFFh
64K MAIN BLOCK
20000h
1FFFFh
64K MAIN BLOCK
10000h
0FFFFh
32K MAIN BLOCK
08000h
07FFFh
8K PARAMETER BLOCK
06000h
05FFFh
8K PARAMETER BLOCK
04000h
03FFFh
16K BOOT BLOCK
Table 3A. M29F002T, M29F002NT Block Address Table
Address Range
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-37FFFh
38000h-39FFFh
3A000h-3BFFFh
3C000h-3FFFFh
A17
0
0
1
1
1
1
1
A16
0
1
0
1
1
1
1
A15
X
X
X
0
1
1
1
A14
X
X
X
X
0
0
1
A13
X
X
X
X
0
1
X
Table 3B. M29F002B Block Address Table
Address Range
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
A17
0
0
0
0
0
1
1
A16
0
0
0
0
1
0
1
A15
0
0
0
1
X
X
X
A14
0
1
1
X
X
X
X
A13
X
0
1
X
X
X
X
4/29
M29F002T, M29F002NT, M29F002B
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signature
or Block Protection Status), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all timing
and verification of the Program and Erase opera-
tions. The Status Register Data Polling, Toggle,
Error bits may be read at any time, during program-
ming or erase, to monitor the progress of the opera-
tion.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instruc-
tions (see Table 8). The third cycle inputs the in-
struction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection, the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Program instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if V
CC
falls below
V
LKO
, the command interface is reset to Read Array.
impedance when the chip is deselected or the
outputs are disabled and when RPNC is at a Low
level.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselects the memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to V
ID
during the Block Unprotection opera-
tion.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
Block Protection and Unprotection operations.
Write Enable (W).
This input controls writing to the
Command Register and Address and Data latches.
Reset/Block Temporary Unprotect/No Connect
Input (RPNC).
The RPNC (not available for the
M29F002NT) input provides hardware reset and
protected block(s) temporary unprotection func-
tions. In read or write mode, the RPNC pin can be
left open (Not Connected) or held at V
IH
. Reset of
the memory is acheived by pulling RPNC to V
IL
for
at least 500ns. When the reset pulse is given, if the
memory is in Read or Standby modes, it will be
available for new operations in 50ns after the rising
edge of RPNC. If the memory is in Erase, Erase
Suspend or Program modes the reset will take
10µs. A hardware reset during an Erase or Program
operation will corrupt the data being programmed
or the sector(s) being erased.
Temporary block unprotection is made by holding
RPNC at V
ID
. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RPNC from V
IH
to V
ID
must slower than
500ns. When RPNC is returned from V
ID
to V
IH
all
blocks temporarily unprotected will be again pro-
tected.
V
CC
Supply Voltage.
The power supply for all op-
erations (Read, Program and Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
DEVICE OPERATIONS
See Tables 4, 5 and 6.
Read.
Read operations are used to output the con-
tents of the Memory Array, the Electronic Signature,
the Status Register or the Block Protection Status.
Both Chip Enable E and Output Enable G must be
low in order to read the output of the memory.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A17).
The address inputs for
the memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to V
ID
, either a Read
Electronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7).
The input is data
to be programmed in the memory array or a com-
mand to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
5/29
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