W29EE512P-12B datasheet, PDF - EEWORLD Datasheet

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W29EE512P-12B: Description64K X 8 CMOS FLASH MEMORY; Categorystorage storage; File Size216KB，22 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W29EE512P-12B Overview

64K X 8 CMOS FLASH MEMORY

W29EE512P-12B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Winbond Electronics Corporation
Parts packaging code	QFJ
package instruction	QCCJ, LDCC32,.5X.6
Contacts	32
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum access time	120 ns
Other features	HARDWARE AND SOFTWARE DATA PROTECTION; 10-YEARS DATA RETENTION; 10K PROGRAM/ERASE CYCLE
command user interface	NO
Data polling	YES
Data retention time - minimum	10
Durability	10000 Write/Erase Cycles
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
memory density	524288 bi
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	512
Number of terminals	32
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6
Package shape	RECTANGULAR
Package form	CHIP CARRIER
page size	128 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	3.56 mm
Department size	128
Maximum standby current	0.0001 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	11.43 mm
Maximum write cycle time (tWC)	10 ms

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W29EE512

64K

8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K

8 bits. The device

can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

is not

required. The unique cell architecture of the W29EE512 results in fast program/erase operations with

extremely low current consumption (compared to other comparable 5-volt flash memory products). The

device can also be programmed and erased using standard EPROM programmers.

FEATURES

•

Single 5-volt program and erase operations

•

Fast page-write operations

•

Low power consumption

−

Active current: 50 mA (max.)

−

Standby current: 100

µA

(max.)

•

Automatic program timing with internal V

−

128 bytes per page

−

Page program cycle: 10 mS (max.)

−

Effective byte-program cycle time: 39

µS

−

Optional software-protected data write

•

Fast chip-erase operation: 50 mS

•

Read access time: 70/90/120 nS

•

Typical page program/erase cycles: 1K/10K

•

Ten-year data retention

•

Software and hardware data protection

generation

•

End of program detection

−

Toggle bit

−

Data polling

•

Latched address and data

•

TTL compatible I/O

•

JEDEC standard byte-wide pinouts

•

Available packages: 32-pin PLCC, TSOP and

VSOP

-1-

Publication Release Date: February 18, 2002

Revision A7

W29EE512

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29EE512 is controlled by #CE and #OE, both of which have to be low for

the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip

is de-selected and only standby power will be consumed. #OE is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.

Refer to the timing waveforms for further details.

Page Write Mode

The W29EE512 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of

data within a page is to be changed, data for the entire page must be loaded into the device. Any byte

that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure

consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the

device. Step 2 is an internal programming cycle, during which the data in the page buffers are

simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,

whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs

first. If the host loads a second byte into the page buffer within a byte-load cycle time (T

BLC

) of 200

µS,

after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes can

then be loaded consecutively. The page load cycle will be terminated and the internal programming

cycle will start if no additional byte is loaded into the page buffer A

to A

specify the page address. All

bytes that are loaded into the page buffer must have the same page address. A

to A

specify the byte

address within the page. The bytes may be loaded in any order; sequential loading is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written

simultaneously into the memory array. Before the completion of the internal programming cycle, the

host is free to perform other tasks such as fetching data from other locations in the system to prepare

to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is

enabled, any write operation requires a series of three-byte program commands (with specific data to a

specific address) to be performed before the data load operation. The three-byte load command

sequence begins the page load cycle, without which the write operation will not be activated. This write

scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise

during system power-up and power-down.

The W29EE512 is shipped with the software data protection enabled. To enable the software data

protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The

device will then enter the software data protection mode, and any subsequent write operation must be

preceded by the three-byte program command cycle. Once enabled, the software data protection will

remain enabled unless the disable commands are issued. A power transition will not reset the software

data protection feature. To reset the device to unprotected mode, a six-byte command sequence is

required.

-3-

Publication Release Date: February 18, 2002

Revision A7

W29EE512

Hardware Data Protection

The integrity of the data stored in the W29EE512 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming and read operation are inhibited when V

less than 2.8V.

(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

Data Polling (DQ

)-Write Status Detection

The W29EE512 includes a data polling feature to indicate the end of a programming cycle. When the

W29EE512 is in the internal programming cycle, any attempt to read DQ

of the last byte loaded during

the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is

completed. DQ

will show the true data.

Toggle Bit (DQ

)-Write Status Detection

In addition to data polling, the W29EE512 provides another method for determining the end of a

program cycle. During the internal programming cycle, any consecutive attempts to read DQ

will

produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's

and 1's will stop. The device is then ready for the next operation.

5-Volt-only Software Chip Erase

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading

cycles, the device enters the internal chip erase mode, which is automatically timed and will be

completed in 50 mS. The host system is not required to provide any control or timing during this

operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment

automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the

software access mode, a six-byte command sequence can be used to access the product ID. A read

from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the

device code (C8h). The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low,

#WE high, and raising A9 to 12 volts.

-4-

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