W29EE011
128K
×
8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K
×
8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
PP
is
not required. The unique cell architecture of the W29EE011 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
•
•
Single 5-volt program and erase operations
Fast page-write operations
−
128 bytes per page
−
Page program cycle: 10 mS (max.)
−
Effective byte-program cycle time: 39
µS
−
Optional software-protected data write
•
Low power consumption
−
Active current: 25 mA (typ.)
−
Standby current: 20
µA
(typ.)
•
•
Automatic program timing with internal V
PP
generation
End of program detection
−
Toggle bit
−
Data polling
•
•
•
•
•
Fast chip-erase operation: 50 mS
Read access time: 90/150 nS
Page program/erase cycles: 1K/10K
Ten-year data retention
Software and hardware data protection
•
•
•
•
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP,
TSOP, and PLCC
-1-
Publication Release Date: July 1999
Revision A12
W29EE011
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29EE011 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs.
CE
is used for device selection. When
CE
is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Page Write Mode
The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing
CE
and
WE
low and
OE
high. The write procedure consists
of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either
CE
or
WE
,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (T
BLC
) of 200
µS,
after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional byte is loaded into the page buffer within 300
µS
(T
BLCO
)
from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last
rising edge of
WE
. A
7
to A
16
specify the page address. All bytes that are loaded into the page buffer
must have the same page address. A
0
to A
6
specify the byte address within the page. The bytes may
be loaded in any order; sequential loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to
a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.
The W29EE011 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the
software data protection feature. To reset the device to unprotected mode, a six-byte command
sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram.
Publication Release Date: July 1999
Revision A12
-3-
W29EE011
Hardware Data Protection
The integrity of the data stored in the W29EE011 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming operation is inhibited when V
DD
is less than
3.8V.
(3) Write Inhibit Mode: Forcing
OE
low,
CE
high, or
WE
high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
Data Polling (DQ
7
)-Write Status Detection
The W29EE011 includes a data polling feature to indicate the end of a programming cycle. When the
W29EE011 is in the internal programming cycle, any attempt to read DQ
7
of the last byte loaded
during the page/byte-load cycle will receive the complement of the true data. Once the programming
cycle is completed. DQ
7
will show the true data.
Toggle Bit (DQ
6
)-Write Status Detection
In addition to data polling, the W29EE011 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ
6
will
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.
5-Volt-only Software Chip Erase
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C1h). The product ID operation can be terminated by a three-byte command sequence.
In the hardware access mode, access to the product ID is activated by forcing
CE
and
OE
low,
WE
high, and raising A9 to 12 volts.
-4-
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