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Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> MC145170D2R2
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MC145170D2R2

Description
PLL FREQUENCY SYNTHESIZER, 185MHz, PDSO16, PLASTIC, SOG-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size236KB，24 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
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MC145170D2R2 Overview

PLL FREQUENCY SYNTHESIZER, 185MHz, PDSO16, PLASTIC, SOG-16

MC145170D2R2 Parametric

Parameter NameAttribute value
MakerMotorola ( NXP )
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Reach Compliance Codeunknown
Analog Integrated Circuits - Other TypesPLL FREQUENCY SYNTHESIZER
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length9.9 mm
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply3/5 V
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.9 mm

MC145170D2R2 Preview

PLL Frequency Synthesizer
with Serial Interface
The new MC145170–2 is pin–for–pin compatible with the MC145170–1. A
comparison of the two parts is shown in the table below. The MC145170–2 is
recommended for new designs and has a more robust power–on reset
(POR) circuit that is more responsive to momentary power supply
interruptions. The two devices are actually the same chip with mask options
for the POR circuit. The more robust POR circuit draws approximately 20
µA
additional supply current. Note that the maximum specification of 100
µA
quiescent supply current has not changed.
The MC145170–2 is a single–chip synthesizer capable of direct usage in
the MF, HF, and VHF bands. A special architecture makes this PLL easy to
program. Either a bit– or byte–oriented format may be used. Due to the
patented BitGrabber™ registers, no address/steering bits are required for
random access
of the three registers. Thus, tuning can be accomplished via
a 2–byte serial transfer to the 16–bit N register.
The device features fully programmable R and N counters, an amplifier at
the fin pin, on–chip support of an external crystal, a programmable reference
output, and both single– and double–ended phase detectors with linear
transfer functions (no dead zones). A configuration (C) register allows the
part to be configured to meet various applications. A patented feature allows
the C register to shut off unused outputs, thereby minimizing noise and
interference.
In order to reduce lock times and prevent erroneous data from being
loaded into the counters, a patented jam–load feature is included. Whenever
a new divide ratio is loaded into the N register, both the N and R counters are
jam–loaded with their respective values and begin counting down together.
The phase detectors are also initialized during the jam load.
•
Operating Voltage Range: 2.7 to 5.5 V
MC145170-2
CMOS PLL FREQUENCY
SYNTHESIZER WITH SERIAL
INTERFACE
SEMICONDUCTOR
TECHNICAL DATA
16
1
P SUFFIX
PLASTIC PACKAGE
CASE 648
16
1
16
1
•
•
•
•
•
•
•
•
Maximum Operating Frequency:
185 MHz @ Vin = 500 mVpp, 4.5 V Minimum Supply
100 MHz @ Vin = 500 mVpp, 3.0 V Minimum Supply
Operating Supply Current:
0.6 mA @ 3.0 V, 30 MHz
1.5 mA @ 3.0 V, 100 MHz
3.0 mA @ 5.0 V, 50 MHz
5.8 mA @ 5.0 V, 185 MHz
Operating Temperature Range: –40 to 85°C
R Counter Division Range: 1 and 5 to 32,767
N Counter Division Range: 40 to 65,535
Direct Interface to Motorola SPI Serial Data Port
See Application Notes AN1207/D and AN1671/D
See web site
mot–sps.com
for MC145170 control software. Select in
order, Products, Wireless Semiconductor, Download, then PLL Demo
Software. Choose PLLGEN.EXE.
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SOG–16)
DT SUFFIX
PLASTIC PACKAGE
CASE 948C
(TSSOP–16)
PIN CONNECTIONS
OSCin
OSCout
REFout
fin
Din
ENB
CLK
Dout
1
2
3
4
5
6
7
8
(Top View)
16 VDD
15
φV
14
φR
13 PDout
12 VSS
11 LD
10 fV
9 fR
BitGrabber is a trademark of Motorola Inc.
COMPARISION OF THE PLL FREQUENCY SYNTHESIZERS
Parameter
Minimum Supply Voltage
Maximum Input Current, fin
Dynamic Characteristics, fin (Figure 23)
Power–On Reset Circuit
MC145170–2
2.7 V
150
µA
Unchanged
Improved
MC145170–1
2.5 V
120
µA
–
–
Device
MC145170P2
MC145170D2
MC145170DT2
TA = –40 to 85°C
ORDERING INFORMATION
Operating
Temp Range
Package
Plastic DIP
SOG–16
TSSOP–16
MC145170–2
4.2–100
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145170–2
BLOCK DIAGRAM
OSCin
OSCout
1
2
OSC
15–stage R Counter
fR Control
9
fR
15
REFout
3
4–Stage
Reference
Divider
BitGrabber R Register
15 Bits
3
Lock Detector
And Control
11
LD
CLK
Din
Dout
6
7
5
Shift
Register
And
Control
Logic
BitGrabber C Register
8 Bits
16
Phase/Frequency
Detector A And Control
13
PDout
8
POR
ENB
Phase/Frequency
Detector B And Control
BitGrabber N Register
16 Bits
16
fin 4
10
14
15
φ
R
φ
V
fV Control
Pin 16 = VDD
Pin 12 = VSS
fV
Input
AMP
16–Stage N Counter
This device contains 4,800 active transistors.
MAXIMUM RATINGS
(Voltages Referenced to VSS)
Parameter
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VDD and VSS Pins
Power Dissipation, per Package
Storage Temperature
Lead Temperature, 1 mm from Case
for 10 seconds
Symbol
VDD
Vin
Vout
Iin
Iout
IDD
PD
Tstg
TL
Value
–0.5 to 5.5
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
±10
±20
±30
300
–65 to 150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
NOTES:
1. Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
2. ESD data available upon request.
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145170–2
4.2–101
MC145170–2
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, TA = –40 to 85°C)
Parameter
Power Supply Voltage Range
Maximum Low–Level Input Voltage [Note 1]
(Din, CLK, ENB, fin)
Minimum High–Level Input Voltage [Note 1]
(Din, CLK, ENB, fin)
Minimum Hysteresis Voltage (CLK, ENB)
Maximum Low–Level Output Voltage
(Any Output)
Minimum High–Level Output Voltage
(Any Output)
Minimum Low–Level Output Current
(PDout, REFout, fR, fV, LD,
φ
R,
φ
V)
Minimum High–Level Output Current
(PDout, REFout, fR, fV, LD,
φ
R,
φ
V)
Minimum Low–Level Output Current
(Dout)
Minimum High–Level Output Current
(Dout)
Maximum Input Leakage Current
(Din, CLK, ENB, OSCin)
Maximum Input Current
(fin)
Maximum Output Leakage Current
(PDout)
(Dout)
Maximum Quiescent Supply Current
Maximum Operating Supply Current
Vin = VDD or VSS; Outputs Open;
Excluding fin Amp Input Current Component
fin = 500 mVpp;
OSCin = 1.0 MHz @ 1.0 Vpp;
LD, fR, fV, REFout = Inactive and No Connect;
OSCout,
φ
V,
φ
R, PDout = No Connect;
Din, ENB, CLK = VDD or VSS
IDD
Idd
Iout = 20
µA
Iout = – 20
µA
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
Vout = 2.4 V
Vout = 4.1 V
Vout = 5.0 V
Vout = 0.4 V
Vout = 4.1 V
Vin = VDD or VSS
Vin = VDD or VSS
Vin = VDD or VSS,
Output in High–Impedance State
dc Coupling to fin
Test Condition
Symbol
VDD
VIL
VDD
V
–
2.7
4.5
5.5
2.7
4.5
5.5
2.7
5.5
2.7
5.5
2.7
5.5
2.7
4.5
5.5
2.7
4.5
5.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
–
Guaranteed
Limit
2.7 to 5.5
0.54
1.35
1.65
2.16
3.15
3.85
0.15
0.20
0.1
0.1
2.6
5.4
0.12
0.36
0.36
–0.12
–0.36
–0.36
1.6
–1.6
±1.0
±150
±100
±5.0
100
[Note 2]
Unit
V
V
dc Coupling to fin
VIH
V
VHys
VOL
VOH
IOL
V
V
V
mA
IOH
mA
IOL
IOH
Iin
Iin
IOZ
mA
mA
µA
µA
nA
µA
µA
mA
NOTES:
1. When dc coupling to the OSCin pin is used, the pin must be driven rail–to–rail. In this case, OSCout should be floated.
2. The nominal values at 3.0 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5.0 V are 3.0 mA @ 50 MHz, and 5.8 mA
@ 185 MHz. These are not guaranteed limits.
MC145170–2
4.2–102
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145170–2
AC INTERFACE CHARACTERISTICS
( TA = –40 to 85°C, CL = 50 pF, Input tr = tf = 10 ns, unless otherwise noted.)
Parameter
Serial Data Clock Frequency (Note: Refer to Clock tw Below)
Symbol
fclk
Figure
No.
1
VDD
V
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
–
–
Guaranteed
Limit
dc to 3.0
dc to 4.0
dc to 4.0
150
85
85
300
200
200
0 to 200
0 to 100
0 to 100
150
50
50
900
150
150
10
10
Unit
MHz
Maximum Propagation Delay, CLK to Dout
tPLH, tPHL
1, 5
ns
Maximum Disable Time, Dout Active to High Impedance
tPLZ, tPHZ
2, 6
ns
Access Time, Dout High Impedance to Active
tPZL, tPZH
2, 6
ns
Maximum Output Transition Time, Dout
CL = 50 pF
tTLH, tTHL
1, 5
ns
CL = 200 pF
1, 5
ns
Maximum Input Capacitance – Din, ENB, CLK
Maximum Output Capacitance – Dout
Cin
Cout
pF
pF
TIMING REQUIREMENTS
( TA = –40 to 85°C, Input tr = tf = 10 ns, unless otherwise noted.)
Parameter
Minimum Setup and Hold Times, Din vs CLK
Symbol
tsu, th
Figure
No.
3
VDD
V
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
Guaranteed
Limit
55
40
40
135
100
100
400
300
300
166
125
125
100
100
100
Unit
ns
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
tsu, th, trec
4
ns
Minimum Inactive–High Pulse Width, ENB
tw(H)
4
ns
Minimum Pulse Width, CLK
tw
1
ns
Maximum Input Rise and Fall Times, CLK
tr, tf
1
µs
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145170–2
4.2–103
MC145170–2
SWITCHING WAVEFORMS
Figure 1.
tf
90%
CLK 50%
10%
tw
1/fclk
tPLH
Dout
90%
50%
10%
tTLH
tTHL
tPHL
tPZH
Dout
50%
tw
Dout
tr
VDD
VSS
ENB
50%
tPZL
50%
Figure 2.
VDD
VSS
tPLZ
10%
tPHZ
90%
VSS
High
Impedance
High
Impedance
VDD
Figure 3.
Valid
VDD
Din
50%
VSS
tsu
CLK
th
50%
VSS
VDD
tsu
CLK
ENB
50%
Figure 4.
tw(H)
VDD
VSS
trec
VDD
50%
First
CLK
Last
CLK
VSS
th
Figure 5. Test Circuit
Test Point
Figure 6. Test Circuit
Test Point
7.5 kΩ
Connect to VDD
when testing tPLZ AND
tPZL. Connect to VSS when
testing tPHZ and tPZH.
Device
Under
Test
CL *
Device
Under
Test
CL *
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
MC145170–2
4.2–104
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
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