CDP1805AC,
CDP1806AC
March 1997
CMOS 8-Bit Microprocessor
with On-Chip RAM† and Counter/Timer
Description
The CDP1805AC and CDP1806AC are functional and per-
formance enhancements of the CDP1802 CMOS 8-bit regis-
ter-oriented microprocessor series and are designed for use
in general-purpose applications.
The CDP1805AC hardware enhancements include a 64-
byte RAM and an 8-bit presettable down counter. The
Counter/Timer which generates an internal interrupt request,
can be programmed for use in timebase, event-counting,
and pulse-duration measurement applications. The
Counter/Timer underflow output can also be directed to the
Q output terminal. The CDP1806AC hardware enhance-
ments are identical to the CDP1805AC, except the
CDP1806AC contains no on-chip RAM.
The CDP1805AC and CDP1806AC software enhancements
include 32 more instructions than the CDP1802. The 32 new
software instructions add subroutine call and return capabil-
ity, enhanced data transfer manipulation, Counter/Timer con-
trol, improved interrupt handling, single-instruction loop
counting, and BCD arithmetic.
Upwards software and hardware compatibility is maintained
when substituting a CDP1805AC or CDP1806AC for other
CDP1800-series microprocessors. Pinout is identical except
for the replacement of V
CC
with ME on the CDP1805AC and
the replacement of V
CC
with V
DD
on the CDP1806AC.
Features
• Instruction Time of 3.2µs, -40
o
C to +85
o
C
• 123 Instructions - Upwards Software Compatible With
CDP1802
• BCD Arithmetic Instructions
• Low-Power IDLE Mode
• Pin Compatible With CDP1802 Except for Terminal 16
• 64K-Byte Memory Address Capability
• 64 Bytes of On-Chip RAM
†
• 16 x 16 Matrix of On-Board Registers
• On-Chip Crystal or RC Controlled Oscillator
• 8-Bit Counter/Timer
n
Ordering Information
CDP1805AC
CDP1805ACE
-
CDP1805ACQ
CDP1805ACD
CDP1805ACDX
CDP1806AC
CDP1806ACE
CDP1806ACEX
CDP1806ACQ
CDP1806ACD
-
-40
o
C to +85
o
C
-40
o
C to +85
o
C
TEMPERATURE RANGE
-40
o
C to +85
o
C
PACKAGE
Plastic DIP
Burn-In
PLCC
SBDIP
Burn-In
N44.65
D40.6
E40.6
PKG. NO.
†
CDP1805AC Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
1370.2
3-38
CDP1805AC, CDP1806AC
Pinouts
CDP1805AC, CDP1806AC
(PDIP, SBDIP)
TOP VIEW
CLOCK
WAIT
CLEAR
Q
SC1
SC0
MRD
BUS 7
BUS 6
1
2
3
4
5
6
7
8
9
40 V
DD
38 DMA IN
V
DD
NC
XTAL
WAIT
SC1
37 DMA OUT
36 INTERRUPT
35 MWR
34 TPA
33 TPB
32 MA7
31 MA6
30 MA5
29 MA4
28 MA3
27 MA2
26 MA1
25 MA0
24 EF1
23 EF2
22 EF3
21 EF4
SC0
MRD
BUS 7
BUS 6
BUS 5
NC
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
MA0
EF4
EF3
EF2
V
SS
EF1
NC
†
N2
N1
N0
CLOCK
CLEAR
INTERRUPT
39
38
37
36
35
34
33
32
31
30
29
39 XTAL
DMA - OUT
DMA - IN
CDP1805AC, CDP1806AC
(PLCC, PACKAGE TYPE Q)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
MWR
TPA
TPB
MA7
MA6
NC
MA5
MA4
MA3
MA2
MA1
BUS 5 10
BUS 4 11
BUS 3 12
BUS 2 13
BUS 1 14
BUS 0 15
†
16
N2 17
N1 18
N0 19
V
SS
20
†
ME for CDP1805AC
V
DD
for CDP1806AC
Schematic
ADDRESS BUS
MA0 - MA7 MRD
IN
CDP1851
PIO
CONTROL
CDP1805AC WITH
RAM, COUNTER/TIMER
CDP1806AC WITH
COUNTER/TIMER
MWR
OUT
BUS0 - BUS7
BUS0 - BUS7
TPA
ME
TPA
MA0 - MA7
Q
MRD
MA0-MA4
CDP1833
1K BYTE ROM
CDP1824
32 BYTE RAM
(USED WITH
CDP1806AC ONLY)
MWR
BUS0 - BUS7
(CDP1805AC ONLY)
CEO
CS
BUS0-BUS4
8-BIT DATA BUS
FIGURE 1. TYPICAL CDP1805AC, CDP1806AC SMALL MICROPROCESSOR SYSTEM
3-39
I/O REQUESTS
MEMORY ADDRESS LINES
MA7 MA5 MA3 MA1
MA6 MA4 MA2 MA0
CLEAR WAIT
EF1 EF3
EF2 EF4
DMA
OUT
DMA
IN INT
I/O FLAGS
CONTROL
ME FOR CDP1805AC
V
DD
FOR CDP1806AC
MUX
64-BYTE
RAM
CONTROL AND
TIMING LOGIC
CLOCK
LOGIC
CDP1805AC
ONLY
CLOCK
COUNTER HOLDING
REGISTER (CH)
MODE
CONTROL
CLK
INTERRUPT
LOGIC
B
(8)
ALU
DF
(1)
R(0).1 R(0).0
R(1).1 R(1).0
R(2).1 R(2).0
R(9).1 R(9).0
R(A).1 R(A).0
R(E).1 R(E).0
R(F).1 R(F).0
REGISTER
ARRAY
R
INCR/
DECR
D
(8)
A
(16)
EF1
EF2
TPA
8-BIT
COUNTER/TIMER
÷
32
TC
INSTRUCTION
DECODE
XTAL
SCO
STATE
CODES
SCI
Q LOGIC
TPA
TPB
SYSTEM
TIMING
MWR
MRD
CDP1805AC, CDP1806AC
FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC
3-40
LATCH
AND
DECODE
X
(4)
8-BIT BIDIRECTIONAL DATA BUS
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
T
(8)
P
(4)
I
(4)
N
(4)
N0
N1
N2
I/O
COMMANDS
CDP1805AC, CDP1806AC
Absolute Maximum Ratings
DC Supply Voltage Range, (V
DD
)
(All Voltages Referenced to V
SS
Terminal). . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, any One Input
. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Information
Thermal Resistance (Typical, Note 2)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
46
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
55
15
Device Dissipation Per Output Transistor
T
A
= Full Package Temperature Range . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T
A
)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Package Type E and Q . . . . . . . . . . . . . . . . . . . . .-40
o
C to +85
o
C
Storage Temperature Range (T
STG
). . . . . . . . . . . .-65
o
C to +150
o
C
Lead Temperature (During Soldering)
At Distance 1/16
±1/32in
(1.59
±
0.79mm) from case for
10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
Printed Circuit Board Mount: 57mm x 57mm Minimum Area x
1.6mm Thick G10 Epoxy Glass, or Equivalent.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
T
A
= Full-Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges.
TEST CONDITIONS
V
DD
(V)
-
-
5
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
MIN
4
V
SS
3.2
MAX
6.5
V
DD
-
UNITS
V
V
µs
Mbyte/s
MHz
PARAMETER
DC Operating Voltage Range
Input Voltage Range
Minimum Instruction Time (Note 1)
(f
CL
= 5MHz)
Maximum DMA Transfer Rate
Maximum Clock Input Frequency,
Load Capacitance (C
L
) = 50pF
Maximum External Counter/Timer Clock
Input Frequency to EF1, EF2
NOTES:
5
5
-
DC
0.625
5
5
DC
2
MHz
1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch, Long Skip, NOP, and “68” family
instructions, which are more than two cycles.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Static Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
±5%,
Except as Noted
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
V
O
(V)
-
0.4
0.4
4.6
4.6
-
-
V
IN
(V)
0, 5
0, 5
5
0, 5
0
0, 5
0, 5
V
DD
(V)
5
5
5
5
5
5
5
(NOTE 3)
TYP
50
4
0.4
-4
-0.2
0
5
PARAMETER
Quiescent Device Current, I
DD
Output Low Drive (Sink) Current, (Except XTAL), I
OL
XTAL Output, I
OL
Output High Drive (Source) Current (Except XTAL, I
OH
XTAL, I
OH
Output Voltage Low Level, V
OL
Output Voltage High Level, V
OH
MIN
-
1.6
0.2
-1.6
-0.1
-
4.9
MAX
200
-
-
-
-
0.1
-
UNITS
µA
mA
mA
mA
mA
V
V
3-41
CDP1805AC, CDP1806AC
Static Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
±5%,
Except as Noted
(Continued)
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
V
O
(V)
0.5, 4.5
0.5, 4.5
V
IN
(V)
-
-
V
DD
(V)
5
5
(NOTE 3)
TYP
-
-
PARAMETER
Input Low Voltage (BUS0 - BUS7, ME), V
IL
Input High Voltage (BUS0 - BUS7, ME), V
IH
Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME)
Positive Trigger Threshold, V
P
Negative Trigger Threshold, V
N
Hysteresis, V
H
Input Leakage Current, I
IN
Three-State Output Leakage Current, I
OUT
Input Capacitance, C
IN
Output Capacitance, C
OUT
Total Power Dissipation (Note 4)
Run
Idle “00” at M (0000)
Minimum Data Retention Voltage, V
DR
Data Retention Current, I
DR
NOTES:
3. Typical values are for T
A
= +25
o
C and nominal V
DD
.
4. External clock: f = 5MHz, t
R
, t
F
= 10ns; C
L
= 50pF.
MIN
-
3.5
MAX
1.5
-
UNITS
V
V
0.5, 4.5
0.5, 4.5
0.5, 4.5
-
0, 5
-
-
-
-
-
0, 5
0, 5
-
-
5
5
5
5
5
-
-
2.2
0.9
0.3
-
-
-
-
2.9
1.9
0.9
±0.1
±0.2
5
10
3.6
2.8
1.6
±5
±5
7.5
15
V
V
V
µA
µA
pF
pF
-
-
-
-
V
DD
= V
DR
V
DD
= 2.4
5
5
-
-
-
-
35
12
2
25
50
18
2.4
100
mW
mW
V
µA
Dynamic Electrical Specifications
at T
A
= -40
o
to +85
o
C; C
L
= 50pF; Input t
R
, t
F
= 10ns; Input Pulse Levels = 0.1V to
V
DD
-0.1V; V
DD
= 5V,
±5%.
CDP1805AC CDP1806AC
(NOTE 5)
TYP
PARAMETER
Propagation Delay Times
Clock to TPA, TPB, t
PLH
, t
PHL
Clock-to-Memory High-Address Byte, t
PLH
, t
PHL
Clock-to-Memory Low-Address Byte, t
PLH
, t
PHL
Clock to MRD, t
PLH
, t
PHL
Clock to MWR, t
PLH
, t
PHL
(See Note 5)
Clock to (CPU DATA to BUS), t
PLH
, t
PHL
Clock to State Code, t
PLH
, t
PHL
Clock to Q, t
PLH
, t
PHL
Clock to N, t
PLH
, t
PHL
Clock to Internal RAM Data to BUS, t
PLH
, t
PHL
Minimum Set-Up And Hold Times (Note 2)
MAX
UNITS
150
325
275
200
150
375
225
250
250
420
275
550
450
325
275
625
400
425
425
650
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-42
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