The ASM2P3805A is a 3.3V, non-inverting clock driver built
using advanced CMOS technology. The device consists of
two banks of drivers, each with a 1:5 fanout and its own
output enable control. The device has a "heartbeat" monitor
for diagnostics and PLL driving. The MON output is
identical to all other outputs and complies with the output
specifications in this document. The ASM2P3805A offers
low capacitance inputs.
The ASM2P3805A is designed for high speed clock
distribution where signal quality and skew are critical. The
ASM2P3805A also allows single point-to-point transmission
line driving in applications such as address distribution,
where one signal must be distributed to multiple receivers
with low skew and high signal quality.
Block Diagram
Pin Diagram
V
CCA
OA
1
1
2
3
4
5
6
7
8
9
10
20 V
CCB
19 OB
1
18 OB
2
17 OB
3
OE
A
IN
A
5
OA
1
– OA
5
OA
2
OA
3
GND
A
OA
4
ASM2P3805A
16 GND
B
15 OB
4
14 OB
5
13 MON
12 OE
B
11 IN
B
IN
B
OE
B
5
OB
1
– OB
5
OA
5
GND
Q
OE
A
MON
IN
A
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
Pin Description
Pin #
9,12
10,11
2,3,4,6,7
19,18,17,15,14
1
20
5
16
8
13
ASM2P3805A
Pin Names
OE
A
, OE
B
¯¯ ¯¯
IN
A
, IN
B
OA
1
-OA
5
OB
1
-OB
5
V
CCA
V
CCB
GND
A
GND
B
GND
Q
MON
Description
3-State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs
Clock Outputs
Power supply for Bank A
Power supply for Bank B
Ground for Bank A
Ground for Bank B
Ground
Monitor Output
Function Table
Inputs
OE
A
, OE
B
¯¯ ¯¯
L
L
H
H
Note: H = HIGH; L = LOW; Z = High-Impedance
Outputs
IN
A
, IN
B
L
H
L
H
OA
n
, OB
n
L
H
Z
Z
MON
L
H
L
H
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
1
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
4.5
5.5
Max
6
8
Unit
pF
pF
Note: 1 This parameter is measured at characterization but not tested.
3.3V CMOS Buffer Clock Driver
Notice: The information in this document is subject to change without notice.
2 of 13
October 2005
rev 0.2
Absolute Maximum Ratings
1
Symbol
V
TERM2
V
TERM3
V
TERM
I
OUT
T
STG
T
J
T
s
T
DV
4
ASM2P3805A
Description
Max
-0.5 to +4.6
-0.5 to +7
-0.5 to V
CC
+0.5
-60 to +60
-65 to +150
150
260
2
Unit
V
V
V
mA
°C
°C
°C
KV
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
DC Output Current
Storage Temperature
Junction Temperature
Max. Soldering Temperature (10 sec)
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
2. V
CC
terminals.
3. Input terminals.
4. Outputs and I/O terminals.
3.3V CMOS Buffer Clock Driver
Notice: The information in this document is subject to change without notice.
3 of 13
October 2005
rev 0.2
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified
Commercial: T
A
= 0°C to +70°C, V
CC
= 3.3V ± 0.3V; Industrial: T
A
= -40 0°C to +85°C, V
CC
= 3.3V ± 0.3V
ASM2P3805A
Symbol
V
IH
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Test Conditions
1
Guaranteed Logic HIGH Level
Min
2
2
Typ
2
-
-
-
-
-
-
-
-
-
-0.7
-60
90
-
3
-
0.2
0.3
-
-135
150
Max
5.5
V
CC
+ 0.5
0.8
±1
±1
±1
±1
±1
±1
-1.2
-110
200
-
-
0.2
0.4
0.5
±1
-240
-
Unit
V
V
IL
I
IH
Input LOW Level
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= 5.5V
V
I
= V
CC
V
CC
= Max.
V
I
= GND
V
I
= GND
V
O
= V
CC
V
O
= GND
-0.5
-
-
-
-
-
-
-
-36
50
V
CC
–0.2
2.4
-
-
-
-
5
V
µA
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
V
CC
= Max.
(3-State Output Pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
µA
V
mA
mA
V
V
CC
= Min., I
IN
= -18mA
V
CC
= 3.3V, V
IN
= V
IH
or
3
V
IL
, V
O
= 1.5V
V
CC
= 3.3V, V
IN
= V
IH
or
3
V
IL
, V
O
= 1.5V
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= -0.1mA
I
OH
= -8mA
I
OL
= 0.1mA
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 16mA
I
OL
= 24mA
V
I
OFF
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Input Power Off Leakage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply
Current
4
V
CC
= 0V, V
IN
= 4.5V
V
CC
= Max., V
O
= GND
-
V
CC
= Max.
V
IN
= GND or V
CC
3
µA
mA
mV
-60
-
-
0.1
10
µA
Notes:1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
- 0.6V at rated current.
3.3V CMOS Buffer Clock Driver
Notice: The information in this document is subject to change without notice.
4 of 13
October 2005
rev 0.2
Power Supply Characteristics
Symbol
∆I
CC
ASM2P3805A
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions
1
V
CC
= Max. V
IN
= V
CC
–0.6V
3
Min
-
Typ
2
10
Max
30
Unit
µA
I
CCD
Dynamic Power Supply Current
4
VCC= Max.
Outputs Open
¯¯
OE
A
=
OE
B
= GND
¯¯
Per Output Toggling
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
-
0.035
0.06
mA/
MHz
V
IN
= V
CC
V
CC
= Max.
V
IN
= GND
Outputs Open
f
O
= 25MHz
50% Duty Cycle
OE
A
=
OE
B
= V
CC
¯¯
¯¯
V
IN
= V
CC-
0.6V
Mon. Output Toggling
V
IN
= GND
I
C
Total Power Supply Current
6
-
0.9
1.6
-
0.9
1.6
mA
V
CC
= Max.
Outputs Open
f
O
= 50MHz
50% Duty Cycle
OE
A
= OE
B
= GND
Eleven Outputs
Toggling
V
IN
= V
CC
V
IN
= GND
-
20
33
5
V
IN
= V
CC-
0.6V
V
IN
= GND
-
20
33
5
Notes:
1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input (V
IN
= V
CC
-0.6V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
C
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT + IINPUTS + IDYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= V
CC
-0.6V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
N
O
= Number of Outputs at f
O
All currents are in milliamps and all frequencies are in megahertz.
3.3V CMOS Buffer Clock Driver
Notice: The information in this document is subject to change without notice.
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