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Datasheet> All Categories > logic> logic> IDT74ALVC16834PA8
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IDT74ALVC16834PA8

Description
Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56
Categorylogic    logic   
File Size65KB，6 Pages
ManufacturerIDT (Integrated Device Technology)
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IDT74ALVC16834PA8 Overview

Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56

IDT74ALVC16834PA8 Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts56
Reach Compliance Codeunknown
seriesALVC/VCX/A
JESD-30 codeR-PDSO-G56
JESD-609 codee0
length14 mm
Logic integrated circuit typeBUS DRIVER
Number of digits18
Number of functions1
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)5.3 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
width6.1 mm

IDT74ALVC16834PA8 Preview

IDT74ALVC16834
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
FEATURES:
DESCRIPTION:
IDT74ALVC16834
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
This 18-bit universal bus driver is built using advanced dual metal CMOS
technology. Data flow from A to Y is controlled by the output-enable (OE).
The device operates in the transparent mode when the latch-enable (LE)
input is low. The A data is latched if the clock (CLK) input is held at a high
or low logic level. If
LE
is high, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When
OE
is high, the outputs are in the
high-impedance state.
The ALVC16834 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
OE
27
CLK
30
LE
28
A
1
54
1
D
3
Y
1
C
1
CLK
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4705/2
IDT74ALVC16834
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
NC
Y
1
GND
Y
2
Y
3
V
CC
Y
4
Y
5
Y
6
GND
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
GND
Y
13
Y
14
Y
15
V
CC
Y
16
Y
17
GND
Y
18
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
C LK
GN D
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
(1)
Inputs
OE
H
L
L
L
L
L
LE
X
L
L
H
H
H
H
CLK
X
X
X
↑
↑
H
L
Ax
X
L
H
L
H
X
X
Outputs
Yx
Z
L
H
L
H
Y
0
Y
0
(2)
(3)
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OE
CLK
LE
Ax
Yx
NC
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Latch Enable (Transparent LOW)
Data Inputs
3-State Outputs
No Internal Connection
2
L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established,
provided that CLK is HIGH before
LE
went HIGH.
3. Output level before the indicated steady-state input conditions were established.
IDT74ALVC16834
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74ALVC16834
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
38
13
V
CC
= 3.3V ± 0.3V
Typical
41
15
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
W
t
SU
t
SU
t
SU
t
H
t
H
t
SK(O)
Propagation Delay
Ax to Yx
Propagation Delay
LE
to Yx
Propagation Delay
CLK to Yx
Output Enable Time
OE
to Yx
Output Disable Time
OE
to Yx
Pulse Duration,
LE
LOW
Pulse Duration, CLK HIGH or LOW
Set-up Time, data before CLK↑
Set-up Time, data before
LE↑,
CLK HIGH
Set-up Time, data before
LE↑,
CLK LOW
Hold Time, data after CLK↑
Hold Time, data after
LE↑,
CLK HIGH or LOW
Output Skew
(2)
3.3
3.3
2.1
2.2
1.5
0.6
0.8
—
—
—
—
—
—
—
—
—
3.3
3.3
2.1
2.3
1.9
0.6
0.8
—
—
—
—
—
—
—
—
—
3.3
3.3
1.7
1.9
1.5
0.7
0.9
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ps
1
4
—
4.7
1.8
4.5
ns
1.4
5.6
—
5.6
1.5
5
ns
1.2
6
—
5.3
1.5
4.6
ns
1.3
6
—
5.9
1.5
4.9
ns
Parameter
Min.
150
1
Max.
—
4.4
V
CC
= 2.7V
Min.
150
—
Max.
—
4.2
V
CC
= 3.3V ± 0.3V
Min.
150
1
Max.
—
3.6
Unit
MHz
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
OUTPUT1 and OUTPUT2 are in the same bank.
For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
For t
SK
(b)
SWITCHING CHARACTERISTICS FROM 0°C TO 65°C, C
L
= 50pF
V
CC
= 3.3V ± 0.15V
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
CLK to xYx
Min.
1.7
Max.
4.3
Unit
ns
4
IDT74ALVC16834
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
500
Ω
Pulse
Generator
(1, 2)
SAME PHASE
INPU T TRAN SITION
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
t
PLH
OU TPUT
t
PLH
OPPOSITE PHASE
INPU T TRAN SITION
t
PHL
6
2.7
1.5
300
300
50
t
PHL
Propagation Delay
ENABLE
CON TROL
IN PUT
t
PZL
DISABLE
V
IN
D .U .T.
V
OUT
V
IH
V
T
0V
V
LOAD/2
V
OL
+ V
LZ
V
OL
V
OH
V
OH -
V
HZ
0V
ALV C Link
t
PLZ
V
LOAD/2
V
T
t
PHZ
V
T
0V
R
T
500
Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
OUTPU T
SW ITCH
NOR MALLY
CLO SED
LOW
t
PZ H
OU TPUT
SW ITCH
NORMALLY
O PE N
H IGH
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
Enable and Disable Times
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
INPU T
V
T
0V
V
OH
OUTPUT 1
V
T
V
OL
V
OH
OUTPUT 2
t
PLH2
t
PHL2
ALVC Link
DATA
INPUT
TIMING
INPU T
ASYNC HRON OU S
CON TROL
SYNC HRON OU S
CON TROL
t
SU
t
H
t
R EM
t
SU
t
H
Set-up, Hold, and Release Times
t
PLH1
t
PHL1
LOW -H IGH -LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
t
SK
(x)
t
SK
(x)
V
T
ALVC Link
V
T
V
OL
Pulse Width
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PH L2
-
t
PHL1
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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IDT74ALVC16834PA8 Related Products

IDT74ALVC16834PA8 IDT74ALVC16834PA IDT74ALVC16834PV8 IDT74ALVC16834PF IDT74ALVC16834PF8
Description Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56 Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56 Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56 Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TVSOP-56 Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TVSOP-56
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP SSOP SSOP SSOP
package instruction TSSOP, TSSOP, TSSOP56,.3,20 SSOP, TSSOP, TSSOP56,.25,16 TSSOP,
Contacts 56 56 56 56 56
Reach Compliance Code unknown not_compliant unknown not_compliant unknown
series ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A
JESD-30 code R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609 code e0 e0 e0 e0 e0
length 14 mm 14 mm 18.415 mm 11.3 mm 11.3 mm
Logic integrated circuit type BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER
Number of digits 18 18 18 18 18
Number of functions 1 1 1 1 1
Number of ports 2 2 2 2 2
Number of terminals 56 56 56 56 56
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP SSOP TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd) 5.3 ns 5.3 ns 5.3 ns 5.3 ns 5.3 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 2.794 mm 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface TIN LEAD Tin/Lead (Sn85Pb15) TIN LEAD Tin/Lead (Sn85Pb15) TIN LEAD
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.635 mm 0.4 mm 0.4 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
width 6.1 mm 6.1 mm 7.5 mm 4.4 mm 4.4 mm

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[i=s]This post was last edited by Jacktang on 2022-1-6 13:15[/i]What is the most widely used power amplifier circuit at present? Answer: The most widely used power amplifier circuits at present are OT...
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