Microelectronics
Inc.
BRIGHT
BM29F400T/BM29F400B
4MEGABIT (512K
×
8/ 256K
×
16)
5VOLT SECTOR ERASE CMOS FLASH MEMORY
GENERAL DESCRIPTION
The BM29F400 is an 4 Megabit, 5.0 volt-only CMOS Flash memory device organized as a 512
Kbytes of 8-bits each, or 256 Kbytes of 16 bits each. The device is offered in standard 48-pin TSOP
package. It is designed to be programmed and erased in-system with a 5.0 volt power-supply and can
also be reprogrammed in standard EPROM programmers.
With access times of 90 nS, 120 nS, and 150 nS, the BM29F400 has separate chip enable CE , write
enable
WE
, and output enable
OE
controls. BMI's memory devices reliably store memory data even
after 100,000 program and erase cycles.
The BM29F400 is entirely pin and command set compatible with the JEDEC standard for 4 Megabit
Flash memory devices. Commands are written to the command register using standard
microprocessor write timings. Register contents serve as input to an internal state-machine which
controls the erase and programming circuitry. Write cycles also internally latch addresses and data
needed for the programming and erase operations.
The BM29F400 is programmed by executing the program command sequence. This will start the
internal byte/word programming algorithm that automatically times the program pulse width and also
verifies the proper cell margin. Erase is accomplished by executing either the sector erase or chip
erase command sequence. This will start the internal erasing algorithm that automatically times the
erase pulse width and also verifies the proper cell margin. No preprogramming is required prior to
execution of the internal erase algorithm. Sectors of the BM29F400 Flash memory array are
electrically erased via Fowler-Nordheim tunneling. Bytes/words are programmed one byte/word at a
time using a hot electron injection mechanism.
The BM29F400 features a sector erase architecture. The device memory array is divided into one 16
Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64 Kbytes. Sectors can be erased individually or in
groups without affecting the data in other sectors. Multiple sector erase and full chip erase capabilities
add flexibility to altering the data in the device. To protect this data from accidental program and
erase, the device also has a sector protect function. This function hardware write protects the
selected sector(s). The sector protect and sector unprotect features can be enabled in a PROM
programmer.
For read, program and erase operation, the BM29F400 needs a single 5.0 volt power-supply.
Internally generated and well regulated voltages are provided for the program and erase operation. A
low Vcc detector inhibits write operations on loss of power. End of program or erase is detected by the
Ready/Busy status pin, Data Polling of DQ7, or by the Toggle Bit I feature on DQ6. Once the program
or erase cycle has been successfully completed, the device internally resets to the Read mode.
The BM29F400 also has a hardware
RESET
pin. Driving the
RESET
pin low during execution of an
Internal Programming or Erase command will terminate the operation and reset the device to the
Read mode. The RESET pin may be tied to the system reset circuitry, so that the system will have
access to boot code upon completion of system reset, even if the Flash device is in the process of an
Internal Programming or Erase operation. If the device is reset using the RESET pin during an
Internal Programming or Erase operation, data in the address locations on which the internal state
A Winbond Company
-1-
Publication Release Date: December 1999
Revision A2
Microelectronics
Inc.
BRIGHT
BM29F400T/BM29F400B
machine is operating will be erroneous. Thus, these address locations will need rewriting after the
device is reset.
FEATURES
•
5.0V +/- 10% Program and Erase
−
Minimizes system-level power requirements
High performance
−
90 nS access time
Compatible with JEDEC-standard Commands
−
Uses software commands, pinouts, and
packages following industry standards for
single power supply Flash memory
Typically 100,000 Program/Erase Cycles
Sector Erase Architecture
−
One 16 Kbytes, two 8 Kbytes, one 32 Kbytes,
and seven 64 Kbytes
−
Any combination of sectors can be erased
concurrently; also supports full chip erase
•
RESET
−
Hardware pin resets the internal state
machine to the read mode
•
•
Internal Erase Algorithms
−
Automatically erases a sector, any
combination of sectors, or the entire
chip
Internal Programming Algorithms
−
Automatically programs and verifies data at a
specified address
Low Power Consumption
−
20 mA typical active read current for Byte
Mode
−
28 mA typical active read current for Word
Mode
−
30 mA typical write/erase current
•
•
•
•
•
Erase Suspend/Resume
−
Suspend a sector erase operation to allow a
data read in a sector not being erased within
the same device
Ready/Busy
−
RY/BY output pin for detection of
programming or erase cycle completion
•
•
Sector Protection
−
Hardware method disables any combination
of sectors from a program or erase operation
Boot Code Sector Architecture
•
FAMILY PART NO.
Maximum Access Time (nS)
CE
(E) Access time (nS)
OE
(G) Access time (nS)
-90
90
90
35
-120
120
120
50
-150
150
150
60
*This speed is available with Vcc = 5V +/- 5% variation
-2-
Microelectronics
Inc.
BRIGHT
BM29F400T/BM29F400B
PIN CONFIGURATIONS
PIN DESCRIPTION
A0−A17
DQ0−DQ14
DQ15/A-1
CE
OE
WE
V
SS
RESET
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
Vss
CE
A0
Standard TSOP
RY/BY
V
CC
BYTE
NC
Address Inputs
Data Input/Output
Data Input/Output, Address
Max.
Chip Enable
Output Enable
Write Enable
Device Ground
Hardware RESET Pin,
Active Low
Ready/Busy Status Output
Device Power Supply
Selects 8-bit or 16-bit Mode
Not Internally Connected
BLOCK DIAGRAM
Vcc
Vss
/WE
/BYTE
/RESET
RY/BY
Buffer
State
Control
Command
Register
DQ0-DQ15
Erase Boltage
Generator
Input/Output
Buffers
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
/CE
/OE
STB
Y-Decodor
Vcc Detector
A0-A16
A-1
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
Timer
A Winbond Company
-3-
Publication Release Date: December 1999
Revision A2
Microelectronics
Inc.
BUS OPERATION
Table 1. Bus Operations
(
BYTE
= V
IH
)
(1)
OPERATION
Electronic ID Manufacturer(2)
Electronic ID Device(2)
Read(3)
Standby
Hardware Reset
Output Disable
Write
Verify Sector Protect(2)
Temporary Sector Unprotect
CE
L
L
L
H
X
L
L
L
X
OE
L
L
L
X
X
H
H
L
X
WE
H
H
H
X
X
H
L
H
X
A0
L
H
A0
X
X
X
A0
L
X
BRIGHT
BM29F400T/BM29F400B
A1
L
L
A1
X
X
X
A1
H
X
A6
L
L
A6
X
X
X
A6
L
X
A9
V
ID
V
ID
A9
X
X
X
A9
V
ID
X
DQ0-DQ15
Code
Code
D
OUT
High Z
High Z
High Z
D
IN
(4)
Code
X
H
H
H
H
L
X
H
H
RESET
V
ID
Notes:
1. L = V
IL
, H = V
IH
, X = Don't Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3.
WE
can be V
IL
if CE is V
IL
,
OE
at V
IH
initiates the write operations.
4. Refer to Table 6 for valid DIN during a write operation.
Table 2. Bus Operations
(
BYTE
= V
IL
)
(1)
OPERATION
Electronic ID Manufacturer(2)
Electronic ID Device(2)
Read(3)
Standby
Hardware Reset
Output Disable
Write
Verify Sector Protect(2)
Temporary Sector Unprotect
CE
L
L
L
H
X
L
L
L
X
OE
L
L
L
X
X
H
H
L
X
WE
A0
L
H
A0
X
X
X
A0
L
X
A1
L
L
A1
X
X
X
A1
H
X
A6
L
L
A6
X
X
X
A6
L
X
A9
V
ID
V
ID
A9
X
X
X
A9
V
ID
X
DQ0-DQ7
Code
Code
D
OUT
High Z
High Z
High Z
D
IN
(4)
Code
X
DQ8-DQ15
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
RESET
H
H
H
H
L
H
H
H
V
ID
H
H
H
X
X
H
L
H
X
Notes:
1. L = V
IL
, H = V
IH
, X = Don't Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3.
WE
can be V
IL
if CE is V
IL
,
OE
at V
IH
initiates the write operations.
4. Refer to Table 6 for valid DIN during a write operation.
-4-
Microelectronics
Inc.
BRIGHT
BM29F400T/BM29F400B
Table 3. Sector Protection Verify Electronic ID Codes
TYPE
Manufacturer Code
29F400T
29F400
29F400B
Sector Protection
Byte
Word
Byte
Word
Sector Address
V
IL
V
IH
V
IL
Note: Outputs 01H at protected sector addresses, and outputs 00H at unprotected addresses.
A17-A12
X
X
X
A6
V
IL
V
IL
V
IL
A1
V
IL
V
IL
V
IL
A0
V
IL
V
IH
V
IH
Code (Hex)
ADH
23H
22,23H
ABH
22 ABH
01H(1)
Table 4. Sector Address Tables (BM29F400T)
A17
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Notes:
1. The address range is A17:A-1 if in byte mode (
BYTE
= V
IL
).
2. The address range is A17:A0, if in word mode (
BYTE
= V
IH
).
0
0
0
0
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
1
1
1
A14
X
X
X
X
X
X
X
0
1
1
1
A13
X
X
X
X
X
X
X
X
0
0
1
A12
X
X
X
X
X
X
X
X
0
1
X
(x8) Address Range
00000H -0FFFFH
10000H -1FFFFH
20000H -2FFFFH
30000H -3FFFFH
4 0000H-4FFFFH
50000H -5FFFFH
60000H -6FFFFH
70000H -77FFFH
78000H -79FFFH
7A000H -7BFFFH
7C000H- 7FFFFH
(x16) Address Range
00000H- 07FFFH
08000H- 0FFFFH
10000H- 17FFFH
18000H- 1FFFFH
20000H- 27FFFH
28000H- 2FFFFH
30000H- 37FFFH
38000H- 3BFFFH
3C000H- 3CFFFH
3D000H- 3DFFFH
3E000H- 3FFFFH
Table 5. Sector Address Tables (BM29F400B)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Notes:
1. The address range is A17:A-1 if in byte mode (
BYTE
= V
IL
).
2. The address range is A17:A0, if in word mode ( BYTE = V
IH
).
A17
0
0
0
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
1
1
0
0
1
1
A15
0
0
0
0
1
0
1
0
1
0
1
A14
0
0
0
1
X
X
X
X
X
X
X
A13
0
1
1
X
X
X
X
X
X
X
X
A12
X
0
1
X
X
X
X
X
X
X
X
(x8) Address Range
00000H-03FFFH
04000H-05FFFH
06000H-07FFFH
08000H-0FFFFH
10000H-1FFFFH
20000H-2FFFFH
30000H-3FFFFH
40000H-4FFFFH
50000H-5FFFFH
60000H-6FFFFH
70000H-7FFFFH
x16) Address Range
00000H-01FFFH
02000H-02FFFH
03000H-03FFFH
04000H-07FFFH
08000H-0FFFFH
10000H-17FFFH
18000H-1FFFFH
20000H-27FFFH
28000H-2FFFFH
30000H-37FFFH
38000H-3FFFFH
A Winbond Company
-5-
Publication Release Date: December 1999
Revision A2
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