128K x 32 EEPROM Module
PUMA 68E4001/A-12/15/20
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.2 : November 1998
Description
The PUMA 68E4001/A is a 4Mbit CMOS
EEPROM module in a JEDEC 68 pin surface
mount PLCC. The plastic device is screened to
ensure high reliability. Access times of 120, 150
and 200ns are available.The output width is user
configurable as 8, 16, or 32 bits wide using CS1-4
and is available in two pinout options, single WE
or WE1-4 (version /A) . Page write (128 bytes) is
performed in 5 ms (typical). The device also
features both hardware and software data protec-
tion with DATA polling and Toggle bit indication of
end of write . Write cycle endurance is 10,000
Erase/Write cycles with a data retention time of 10
years.
4,194,304 bit CMOS EEPROM Module
Features
· Access Times of 120/150/200 ns.
· User Configurable as 8 / 16 / 32 bit wide output.
· Commercial, Industrial, or Military grades.
· Operating Power
490 / 913 / 1760 mW (max).
· JEDEC 68 pin surface mount PLCC, available in two
pinouts : Single WE, WE1~4 is version A.
· High reliability plastic design
· Hardware and Software Data Protection.
· Endurance of 10
4
Erase/Write Cycles and Data
Retention Time of 10 years.
Block Diagram
(see page 11 for Block Diagram of option /A)
Pin Definition
(see page 11 for option /A Pinout)
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
VCC
A0~A16
OE
WE
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
VIEW
18
52
19
51
FROM
20
50
ABOVE
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68E4001
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
Pin Functions
A0~16
Address Inputs
CS1~4
Chip Select
WE
Write Enable (WE1~4 on version A)
V
CC
Power (+5V)
D0~31
OE
NC
GND
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
NC
NC
NC
NC
NC
GND
NC
Data Inputs/Outputs
Output Enable
No Connect
Ground
ISSUE 4.2 : November 1998
PUMA 68E4001/A-12/15/17/20
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Operating Temperature
Storage Temperature
Input voltages (including N.C. pins) with Respect to GND
Output voltages with respect to GND
T
OPR
T
STG
V
IN
V
OUT
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to V
CC
+0.6
C
°
C
V
V
°
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
min
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
V
CC
V
IL
V
IH
T
A
T
AI
T
AM
4.5
-1.0
2.0
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
0.8
V
CC
+1
70
85
125
V
V
V
°
C
°
C (I Suffix)
°
C (M Suffix)
DC Electrical Characteristics
(T
A
=-55°C to +125°C,V
CC
=5V ± 10%)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Symbol
I
LI1
32 bit I
LO
32 bit I
CC32
16 bit I
CC16
8 bit I
CC8
Test Condition
min
-
-
-
-
-
-
-
-
2.4
max
40
40
320
166
89
12
1.2
0.45
-
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
V
IN
= GND to V
CC
+1
V
I/O
= GND to V
CC
, CS
(1)
=V
IH
CS
(1)
=OE=V
IL
, WE=V
IH
, I
OUT
=0mA, ƒ=5MHz
(2)
As above
As above
CS
(1)
= 2.0V to V
CC
+1V
CS
(1)
= V
CC
-0.3V to V
CC
+1V
I
OL
= 2.1mA.
I
OH
= -400µA.
Standby Supply Current TTL levels I
SB1
CMOS levels I
SB2
Output Low Voltage
Output High Voltage
V
OL
V
OH
Notes (1) CS above are accessed through CS1-4. These inputs must be operated simultaneously for 32 bit operation, in pairs
in 16 bit mode and singly for 8 bit mode.
(2) Also for WE1~4 on the PUMA 68E4001A version. Additionally, WE1~4 are accessed as in note (1) above.
Capacitance
(T
A
=25°C,ƒ=1MHz)
Note: These parameters are calculated, not measured.
Parameter
Input Capacitance
Output Capacitance
CS1~4, WE1~4
(1)
Other Inputs
Symbol
C
IN1
C
IN2
C
OUT
Test Condition
V
IN
=0V
V
IN
=0V
V
OUT
=0V
typ
-
-
-
max Unit
20
22
22
pF
pF
pF
Notes: (1) On the PUMA 68E4001A version only.
2
PUMA 68E4001/A-12/15/17/20
ISSUE 4.2 : November
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable Access Time
Chip Select High to High Z Output (1)
Chip Select Low to Active Output (1)
12
Symnbol min max
t
RC
t
AA
t
CS
t
OE
t
HZ
t
LZ
t
OLZ
t
OH
120
-
-
0
0
0
0
0
0
-
120
120
60
50
50
-
-
-
15
min max
150
-
-
0
0
0
0
0
0
-
150
150
70
50
50
-
-
-
20
min
200
-
-
0
0
0
0
0
0
max
-
200
200
80
50
50
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable High to High Z Output (1) t
OHZ
Output Enable Low to Active Output (1)
Output Hold from Address Change
Notes: (1) t
HZ
max. and t
OLZ
max. are measured with CL = 5pF, from the point when Chip Select or Output Enable return high
(whichever occurs first) to the time when the outputs are no longer driven. t
HZ
and t
OHZ
are shown for reference only:
they are characterized and not tested.
Write Cycle
Parameter
Write Cycle Time
Address Set-up Time
Address Hold Time
Output Enable Set-up Time
Output Enable Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width
Write Enable High Recovery
Data Set-up Time
Data Hold Time
Delay to Next Write
Byte Load Cycle
AC Test Conditions
Symbol
t
WC
t
AS
t
AH
t
OES
t
OEH
t
CS
t
CH
t
WP
t
WPH
t
DS
t
DH
t
DW
t
BLC
min
-
0
50
0
0
0
0
100
50
50
0
10
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
max
10
-
-
-
-
-
-
-
-
-
-
-
150
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Output Test Load
I/O Pin
645
Ω
1.76V
100pF
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 10ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* V
CC
=5V±10%
1998
ISSUE 4.2 : November 1998
PUMA 68E4001/A-12/15/17/20
Read Cycle Timing Waveform
t
RC
Address Valid
A0~A16
t
AA
CS1~4
t
OHZ
t
CS
t
OE
OE
t
OHZ
t
OLZ
t
OH
Output
Valid
Data
HIGH Z
t
CLZ
AC Write Waveform - WE Controlled
t
WC
Address
t
AS
WE
t
AH
t
WP
t
WPH
t
CS
CS1~4
t
CH
t
OES
OE
t
OEH
DATA
t
DS
t
DH
4
PUMA 68E4001/A-12/15/17/20
ISSUE 4.2 : November
AC Write Waveform - CS Controlled
t
WC
Address
t
AS
t
CS
WE
t
AH
t
CH
t
WP
CS1~4
t
OES
OE
t
WPH
t
OEH
DATA
t
DS
t
DH
Page Mode Write Waveform
OE
CS1~4
t
WP
t
WPH
t
BLC
WE
t
AS
t
AH
Valid
Add
t
DH
A0-A16
t
DS
Data
Valid
Data
Byte 0
Byte 1
Byte 2
Byte 3
Byte 126
Byte 127
t
WC
Note: A8 through A16 must specify the page address during each high to low transition of Write Enable (or Chip select).
Output Enable must be high only when Write Enable and Chip Select are both low.
1998
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EEWORLD
