M29F200BT70M1 datasheet, PDF - EEWORLD Datasheet

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M29F200BT70M1: Description128KX16 FLASH 5V PROM, 70ns, PDSO44, 0.525 INCH, PLASTIC, SOP-44; Categorystorage storage; File Size196KB，22 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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M29F200BT70M1 Overview

128KX16 FLASH 5V PROM, 70ns, PDSO44, 0.525 INCH, PLASTIC, SOP-44

M29F200BT70M1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	0.525 INCH, PLASTIC, SOP-44
Contacts	44
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	70 ns
Other features	TOP BOOT BLOCK
Spare memory width	8
startup block	TOP
command user interface	YES
Data polling	YES
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G44
JESD-609 code	e3
length	28.5 mm
memory density	2097152 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	1,2,1,3
Number of terminals	44
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP44,.63
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	3 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.0001 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	12.6 mm

M29F200BT70M1 Preview

M29F200BT

M29F200BB

2 Mbit (256Kb x8 or 128Kb x16, Boot Block)

Single Supply Flash Memory

SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 45ns

PROGRAMMING TIME

– 8µs per Byte/Word typical

7 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location)

– 2 Parameter and 4 Main Blocks

PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Polling and Toggle Bits

– Ready/Busy Output Pin

TSOP48 (N)

12 x 20mm

SO44 (M)

ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

Figure 1. Logic Diagram

UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

TEMPORARY BLOCK UNPROTECTION

MODE

LOW POWER CONSUMPTION

– Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per

BLOCK

20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– Top Device Code M29F200BT: 00D3h

– Bottom Device CodeM29F200BB: 00D4h

A0-A16

VCC

DQ0-DQ14

DQ15A–1

M29F200BT

M29F200BB

BYTE

VSS

AI02912

July 2000

1/22

M29F200BT, M29F200BB

Figure 2. TSOP Connections

A15

A14

A13

A12

A11

A10

A16

BYTE

VSS

DQ15A–1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

VSS

Figure 3. SO Connections

M29F200BT

M29F200BB

VSS

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

11 M29F200BT 34

12 M29F200BB 33

AI02914

A10

A11

A12

A13

A14

A15

A16

BYTE

VSS

DQ15A–1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

AI02913

Table 1. Signal Names

A0-A16

DQ0-DQ7

DQ8-DQ14

DQ15A–1

BYTE

2/22

Address Inputs

Data Inputs/Outputs

Data Input/Output or Address Input

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

Ground

Not Connected Internally

SUMMARY DESCRIPTION

The M29F200B is a 2 Mbit (256Kb x8 or 128Kb

x16) non-volatile memory that can be read, erased

and reprogrammed. These operations can be per-

formed using a single 5V supply. On power-up the

memory defaults to its Read mode where it can be

read in the same way as a ROM or EPROM. The

M29F200B is fully backward compatible with the

M29F200.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

M29F200BT, M29F200BB

Table 2. Absolute Maximum Ratings

(1)

Symbol

Parameter

Ambient Operating Temperature (Temperature Range Option 1)

Ambient Operating Temperature (Temperature Range Option 6)

Ambient Operating Temperature (Temperature Range Option 3)

BIAS

STG

IO (2)

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

Identification Voltage

Value

0 to 70

–40 to 85

–40 to 125

–50 to 125

–65 to 150

–0.6 to 6

–0.6 to 13.5

Unit

°C

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

The blocks in the memory are asymmetrically ar-

ranged, see Tables 3 and 4, Block Addresses. The

first or last 64 Kbytes have been divided into four

additional blocks. The 16 Kbyte Boot Block can be

used for small initialization code to start the micro-

processor, the two 8 Kbyte Parameter Blocks can

be used for parameter storage and the remaining

32K is a small Main Block where the application

may be stored.

Table 3. Top Boot Block Addresses,

M29F200BT

Size

(Kbytes)

Address Range

(x8)

3C000h-3FFFFh

3A000h-3BFFFh

38000h-39FFFh

30000h-37FFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

Address Range

(x16)

1E000h-1FFFFh

1D000h-1DFFFh

1C000h-1CFFFh

18000h-1BFFFh

10000h-17FFFh

08000h-0FFFFh

00000h-07FFFh

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm)

and SO44 packages and it is supplied with all the

bits erased (set to ’1’).

Table 4. Bottom Boot Block Addresses,

M29F200BB

Size

(Kbytes)

Address Range

(x8)

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

08000h-0FFFFh

06000h-07FFFh

04000h-05FFFh

00000h-03FFFh

Address Range

(x16)

18000h-1FFFFh

10000h-17FFFh

08000h-0FFFFh

04000h-07FFFh

03000h-03FFFh

02000h-02FFFh

00000h-01FFFh

3/22

M29F200BT, M29F200BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A16).

The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7).

The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Data Inputs/Outputs (DQ8-DQ14).

The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation when BYTE

is High, V

. When BYTE is Low, V

, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, V

, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, V

, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to include this pin when BYTE is Low except

when stated explicitly otherwise.

Chip Enable (E).

The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, V

, all other pins are ignored.

Output Enable (G).

The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W).

The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP).

The Re-

set/Block Temporary Unprotect pin can be used to

apply a Hardware Reset to the memory or to tem-

porarily unprotect all Blocks that have been pro-

tected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block temporary unprotect goes

High, V

, the memory will be ready for Bus Read

and Bus Write operations after t

PHEL

or t

RHEL

whichever occurs last. See the Ready/Busy Out-

put section, Table 17 and Figure 11, Reset/Tem-

porary Unprotect AC Characteristics for more

details.

Holding RP at V

will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V

to V

must be slower than

PHPHH

Ready/Busy Output (RB).

The Ready/Busy pin

is an open-drain output that can be used to identify

when the memory array can be read. Ready/Busy

is high-impedance during Read mode, Auto Select

mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 17 and Figure

11, Reset/Temporary Unprotect AC Characteris-

tics.

During Program or Erase operations Ready/Busy

is Low, V

. Ready/Busy will remain Low during

Read/Reset commands or Hardware Resets until

the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE).

The Byte/

Word Organization Select pin is used to switch be-

tween the 8-bit and 16-bit Bus modes of the mem-

ory. When Byte/Word Organization Select is Low,

, the memory is in 8-bit mode, when it is High,

, the memory is in 16-bit mode.

Supply Voltage.

The V

Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, I

CC4

Vss Ground.

The V

Ground is the reference

for all voltage measurements.

4/22

M29F200BT, M29F200BB

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Tables 5 and 6, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Bus Read.

Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable

High, V

. The Data Inputs/Outputs will output the

value, see Figure 8, Read Mode AC Waveforms,

and Table 14, Read AC Characteristics, for details

of when the output becomes valid.

Table 5. Bus Operations, BYTE = V

Operation

Bus Read

Bus Write

Output Disable

Standby

Read Manufacturer

Code

Read Device Code

Note: X = V

or V

Bus Write.

Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, V

, during the whole Bus

Write operation. See Figures 9 and 10, Write AC

Waveforms, and Tables 15 and 16, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable.

The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, V

Address Inputs

DQ15A–1, A0-A16

Cell Address

Command Address

A0 = V

, A1 = V

, A9 = V

Others V

or V

A0 = V

, A1 = V

, A9 = V

Others V

or V

Data Inputs/Outputs

DQ14-DQ8

Hi-Z

DQ7-DQ0

Data Output

Data Input

Hi-Z

20h

D3h (M29F200BT)

D4h (M29F200BB)

Table 6. Bus Operations, BYTE = V

Operation

Bus Read

Bus Write

Output Disable

Standby

Read Manufacturer

Code

Read Device Code

Note: X = V

or V

Address Inputs

A0-A16

Cell Address

Command Address

A0 = V

, A1 = V

, A9 = V

Others V

or V

A0 = V

, A1 = V

, A9 = V

Others V

or V

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Data Output

Data Input

Hi-Z

0020h

00D3h (M29F200BT)

00D4h (M29F200BB)

5/22

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