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CAT24C208PI

Description
EEPROM, 1KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8
Categorystorage    storage   
File Size116KB,16 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT24C208PI Overview

EEPROM, 1KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8

CAT24C208PI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCatalyst
Parts packaging codeDIP
package instructionDIP,
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum clock frequency (fCLK)0.4 MHz
JESD-30 codeR-PDIP-T8
JESD-609 codee0
length9.59 mm
memory density8192 bit
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals8
word count1024 words
character code1000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1KX8
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialSERIAL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height4.57 mm
Serial bus typeI2C
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.62 mm
Maximum write cycle time (tWC)5 ms
Advance Information
CAT24C208
FEATURES
s
400 kHz I
2
C bus compatible*
s
Complies with VESA E-EDID, E-DDC, DI-EXT
8K (1K x 8) -Bit Dual Port Serial EEPROM for VESA Plug and Play Applications
LE
in LCD Projectors and Monitors
A
D
F
R
E
E
TM
s
1,000,000 program/erase cycles
s
100 year data retention
s
8-pin DIP, SOIC, TSSOP or MSOP packages
and M1 specifications
s
3V to 5.5V volt operation
s
Low power CMOS technology
s
16-byte page write buffer
s
Self-timed write cycle with auto-clear
- Green package option
s
Industrial and extended temperature ranges
DESCRIPTION
The CAT24C208 is an 8k-bit Dual Port Serial CMOS
EEPROM internally organized as 1k words of 8 bits
each. The CAT24C208 features a 16-byte page write
buffer and can be accessed from either of two separate
I
2
C compatible ports, DSP (SDA, SCL) and DDC (SDA,
SCL) which conform to the VESA E-EDID EEPROM
Standard.
Arbitration between the two interface ports is automatic
and allows the appearance of individual access to the
memory from each interface.
Using Catalyst's advanced CMOS technology which
substantially reduces device power requirements, the
CAT24C208 can be powered from either of two
independent V
CC
inputs.
The CAT24C208 operates over the full industrial and
extended temperature range and is available in
miniature 8-pin DIP, SOIC, TSSOP and MSOP
packages.
BLOCK DIAGRAM
DSP VCC
ARBITRATION
LOGIC
DDC VCC
DSP SCL
DSP SDA
DISPLAY
CONTROL
LOGIC
D
E
C
O
D
E
R
S
1K X 8
MEMORY
ARRAY
D
E
C
O
D
E
R
S
DDC
CONTROL
LOGIC
VSS
CONFIGURATION
REGISTER
EDID SEL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1044, Rev. D
1
H
GEN
FR
ALO
EE
DDC SCL
DDC SDA
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