K4S280832B-NL1H datasheet, PDF

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K4S280832B-NL1H: DescriptionSynchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54; Categorystorage storage; File Size64KB，8 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4S280832B-NL1H Overview

Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54

K4S280832B-NL1H Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP,
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
length	11.2 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	54
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	DUAL
width	10.16 mm

K4S280832B-NL1H Preview

shrink-TSOP

K4S280832B-N

4M x 8Bit x 4 Banks Synchronous DRAM in sTSOP

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

- CAS latency (2 & 3)

- Burst length (1, 2, 4, 8 & Full page)

- Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

CMOS SDRAM

GENERAL DESCRIPTION

The K4S280832B-N is 134,217,728 bits synchronous high

data rate Dynamic RAM organized as 4 x 4,194,304 words by 8

bits, fabricated with SAMSUNG′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programma-

ble burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

ORDERING INFORMATION

Part No.

K4S280832B-NC/L1H

K4S280832B-NC/L1L

Max Freq.

100MHz(CL=2)

100MHz(CL=3)

Interface Package

LVTTL

54pin

sTSOP(II)

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

Data Input Register

LDQM

Bank Select

4M x 8

Refresh Counter

Output Buffer

Row Decoder

Sense AMP

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

Latency & Burst Length

LRAS

LCBR

LCKE

LRAS

LCBR

LWE

LCAS

Programming Register

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to change products or specification without notice.

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K4S280832B-N

PIN CONFIGURATION

(Top view)

DQ0

DDQ

N.C

DQ1

SSQ

N.C

DQ2

DDQ

N.C

DQ3

SSQ

N.C

CAS

RAS

BA0

BA1

A10/AP

DQ7

SSQ

N.C

DQ6

DDQ

N.C

DQ5

SSQ

N.C

DQ4

DDQ

N.C

N.C/RFU

DQM

CLK

CKE

N.C

A11

CMOS SDRAM

54Pin sTSOP

(400mil x 441mil)

(0.4 mm Pin pitch)

PIN FUNCTION DESCRIPTION

CLK

Name

System clock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.

Row address : RA

~ RA

, Column address : CA

~ CA

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

This pin is recommended to be left No Connection on the device.

CKE

Clock enable

~ A

~ BA

RAS

CAS

DQM

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Data output power/ground

No connection

/reserved for future use

DDQ

SSQ

N.C/RFU

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K4S280832B-N

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

, V

DDQ

STG

Value

-1.0 ~ 4.6

-55 ~ +150

Unit

°C

CMOS SDRAM

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Symbol

, V

DDQ

Min

3.0

2.0

-0.3

2.4

-10

Typ

3.3

3.0

Max

3.6

+0.3

0.8

0.4

Unit

= -2mA

= 2mA

Note

Notes :

1. V

(max) = 5.6V AC.The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

Clock

= 3.3V, T

= 23°C, f = 1MHz, V

REF

=1.4V

200 mV)

Symbol

CLK

ADD

OUT

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

RAS, CAS, WE, CS, CKE, DQM

Address

~ DQ

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K4S280832B-N

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T

= 0 to 70°C)

Parameter

Symbol

Burst length = 1

≥

(min)

= 0 mA

CKE

≤

(max), t

= 10ns

CKE & CLK

≤

(max), t

∞

CKE

≥

(min), CS

≥

(min), t

= 10ns

Input signals are changed one time during 20ns

CKE

≥

(min), CLK

≤

(max), t

∞

Input signals are stable

CKE

≤

(max), t

= 10ns

CKE & CLK

≤

(max), t

∞

CKE

≥

(min), CS

≥

(min), t

= 10ns

Input signals are changed one time during 20ns

CKE

≥

(min), CLK

≤

(max), t

∞

Input signals are stable

= 0 mA

Page burst

4Banks Activated

CCD

= 2CLKs

≥

(min)

CKE

≤

0.2V

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S280832B-NC**

4. K4S280832B-NL**

5. Unless otherwise noted, input swing IeveI is CMOS(V

DDQ

SSQ)

Test Condition

-1H

Operating current

(One bank active)

Precharge standby current in

power-down mode

CC1

CC2

Precharge standby current in

non power-down mode

CC2

Active standby current in

power-down mode

CC3

110

Version

-1L

Unit

Note

CMOS SDRAM

Active standby current in

non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

CC4

125

CC5

CC6

210

1.5

800

shrink-TSOP

K4S280832B-N

AC OPERATING TEST CONDITIONS

= 3.3V

0.3V, T

= 0 to 70°C)

Parameter

AC input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

3.3V

CMOS SDRAM

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

Vtt = 1.4V

Unit

1200Ω

Output

870Ω

50pF

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I

= 2mA

Output

Z0 = 50Ω

50Ω

50pF

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Row active to row active delay

RAS to CAS delay

Row precharge time

Row active time

Row cycle time

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

Col. address to col. address delay

Number of valid output data

Symbol

-1H

RRD

(min)

RCD

(min)

RAS

(min)

RAS

(max)

(min)

RDL

(min)

DAL

(min)

CDL

(min)

BDL

(min)

CCD

(min)

CAS latency=3

CAS latency=2

100

2 CLK + 20 ns

Version

-1L

CLK

2,5

Unit

Note

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. tRDL=1CLK and tDAL=1CLK+20ns is also supported .

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.

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K4S280832B-NL1H Related Products

	K4S280832B-NL1H	K4S280832B-NL1L	K4S280832B-NC1H	K4S280832B-NC1L
Description	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP,	TSOP,	TSOP,	TSOP,
Contacts	54	54	54	54
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
length	11.2 mm	11.2 mm	11.2 mm	11.2 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	8	8	8	8
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	54	54	54	54
word count	16777216 words	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	16MX8	16MX8	16MX8	16MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP	TSOP	TSOP	TSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.4 mm	0.4 mm	0.4 mm	0.4 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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