shrink-TSOP
K4S280832C-N
4M x 8Bit x 4 Banks Synchronous DRAM in sTSOP
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S280832C-N is 134,217,728 bits synchronous high
data rate Dynamic RAM organized as 4 x 4,194,304 words by 8
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part No.
K4S280832C-NC/L75
K4S280832C-NC/L1H
K4S280832C-NC/L1L
Max Freq.
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
LVTTL
Interface Package
54
sTSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
4M x 8
4M x 8
4M x 8
4M x 8
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 September 2000
shrink-TSOP
K4S280832C-N
PIN CONFIGURATION
(Top view)
V
D D
DQ0
V
DDQ
N.C
DQ1
V
SSQ
N.C
DQ2
V
DDQ
N.C
DQ3
V
SSQ
N.C
V
D D
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
D D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SSQ
N.C
DQ6
V
DDQ
N.C
DQ5
V
SSQ
N.C
DQ4
V
DDQ
N.C
V
SS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
CMOS SDRAM
54Pin sTSOP
(400mil x 441mil)
(0.4 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A
0
~ A
11
BA
0
~ BA
1
RAS
CAS
WE
DQM
DQ
0
~
7
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
Rev. 0.1 September 2000
shrink-TSOP
K4S280832C-N
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
S T G
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Unit
V
V
°C
W
mA
CMOS SDRAM
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C )
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
, V
DDQ
V
IH
V
IL
V
O H
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
I H
(max) = 5.6V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Note
1
2
2
3
RAS, CAS, WE, CS, CKE, DQM
Address
D Q
0
~ DQ
7
Rev. 0.1 September 2000
shrink-TSOP
K4S280832C-N
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70°C)
Parameter
Sym-
bol
Burst length = 1
t
RC
≥
t
R C
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
C
L
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S280832C-NC**
4. K4S280832C-NL**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Test Condition
-75
120
Version
-1H
110
-1L
110
mA
1
Unit
Note
CMOS SDRAM
Operating current
(One bank active)
Precharge standby current in
power-down mode
I
CC1
I
CC2
P
I
C C 2
PS
I
CC2
N
1
1
20
mA
Precharge standby current in
non power-down mode
I
CC2
NS
Active standby current in
power-down mode
I
CC3
P
I
C C 3
PS
I
CC3
N
mA
7
5
5
30
mA
mA
Active standby current in
non power-down mode
(One bank active)
I
CC3
NS
20
mA
Operating current
(Burst mode)
Refresh current
Self refresh current
I
CC4
150
125
125
mA
1
I
CC5
I
CC6
220
210
1.5
800
210
mA
mA
uA
2
3
4
Rev. 0.1 September 2000
shrink-TSOP
K4S280832C-N
AC OPERATING TEST CONDITIONS
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
CMOS SDRAM
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°C)
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Vtt = 1.4V
Unit
V
V
ns
V
1200
Ω
Output
870Ω
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Output
Z0 = 50
Ω
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Symbol
- 75
t
RRD
(min)
t
RCD
(min)
t
R P
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
-
65
15
20
20
45
Version
- 1H
20
20
20
50
100
70
2
2 CLK + 20 ns
1
1
1
2
1
70
-1L
20
20
20
50
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
1
2,5
5
2
2
3
4
1
1
1
1
Unit
Note
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.1 September 2000
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