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P1812A-08SR

Description
Clock Generator, 70MHz, CMOS, PDSO8, SOIC-8
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size121KB,6 Pages
ManufacturerPulseCore Semiconductor Corporation
Download Datasheet Parametric Compare View All

P1812A-08SR Overview

Clock Generator, 70MHz, CMOS, PDSO8, SOIC-8

P1812A-08SR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerPulseCore Semiconductor Corporation
package instructionSOIC-8
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-G8
length4.92 mm
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency70 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Master clock/crystal nominal frequency35 MHz
Certification statusNot Qualified
Maximum seat height1.8 mm
Maximum supply voltage3.7 V
Minimum supply voltage2.7 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.95 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER

P1812A-08SR Preview

PRELIMINARY Specification
Alliance Semiconductor®
P1812A
Low Power Spread Spectrum Clock Multiplier
FEATURES
FCC approved method of EMI attenuation
Generates a
2X
low EMI spread spectrum
signal of the input clock frequency
Optimized for input frequency range from
10 to 35 MHz
Internal loop filter minimizes external
components and board space
2 selectable spread ranges
Low inherent cycle-to-cycle jitter
3.3V operating voltage
CMOS/TTL compatible inputs and outputs
Ultra low power
CMOS design
TBD mA @3.3V, 20 MHz
TBD mA @3.3V, 40 MHz
TBD mA @3.3V, 66 MHz
Pinout compatible to Cypress CY25812
SSON/SBM pin for Spread Spectrum On/Off
and Standby Mode controls
Available in 8 pin SOIC and TSSOP
PRODUCT DESCRIPTION
The P1812A is a spread spectrum frequency
multiplier designed specifically to accept
externally generated clock, crystal and ceramic
resonator for input frequency range from 10 –
35MHz and outputs a 2X low EMI clock with
frequency range from 20 – 70MHz. The P1812A
reduces EMI at the clock source, allowing system
wide reduction of EMI of down stream (clock and
data dependent signals). The P1812A allows
significant system cost savings by eliminating the
use of expensive high frequency OSC and
reducing the number of circuit board layers and
shielding that are traditionally required to pass
EMI regulations.
The P1812A modulates the output of a single PLL
in order to “spread” the bandwidth of a
synthesized clock, thereby decreasing the peak
amplitudes of its harmonics. This results in
significantly lower system EMI compared to the
typical narrow band signal produced by oscillators
and most clock generators. Lowering EMI by
increasing a signal’s bandwidth is called “spread
spectrum clock generation”.
The P1812A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all-digital
method.
APPLICATIONS
The P1812A is targeted towards printers, MFPs,
LCD scalers, Copiers, PDAs, storage devices,
scanners, faxes, embedded processor, and DSP
applications
Figure 1 - P1812A Pin Diagram
CLKIN
VSS
FS0
SSON/
SBM
1
2
3
4
8
7
6
5
XOUT
VDD
SR0
ModOut
May, 2002
Revision C
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
1 of 1
PRELIMINARY Specification
Alliance Semiconductor®
Figure 2 - P1812A Block Diagram
SR0 FS0 SSON
VDD
P1812A
Modulation
XIN
XOUT
Feedback
Divider
Crystal
Oscillator
Frequency
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
P1812 Block Diagram
VSS
CLKIN
Disable
d
Disable
d
Enabled
Enabled
SSON/SBM
0
1
0
1
Table 1- Standby Mode Selection
Spread Spectrum
ModOut
N/A
Disabled
N/A
OFF
ON
Disabled
Reference
2X
PLL
Disabled
Free Running
Disabled
Normal
Mode
Standby
Free Running
Buffer Out
Normal
FS0
1
1
0
0
SR0
0
1
0
1
Table 2 - Spread Range Selection
Spreading Range Input Frequency
Output Frequency
+/- 1.25%
10 MHz to 20 MHz 20 MHz to 40 MHz
+/- 2.00%
10 MHz to 20 MHz 20 MHz to 40 MHz
+/- 1.25%
20 MHz to 35 MHz 40 MHz to 70 MHz
+/- 2.00%
20 MHz to 35 MHz 40 MHz to 70 MHz
Modulation rate
(Fin/10)*20.83 KHz
(Fin/10)*20.83 KHz
(Fin/10)*20.83 KHz
(Fin/10)*20.83 KHz
PIN DESCRIPTION
PIN #
Name
1
CLKIN
Type
I
2
3
4
5
6
7
8
May, 2002
Revision C
VSS
FS0
SSON/SB
M
ModOUT
SR0
VDD
XOUT
P
I
I
O
I
P
I
Description
Connect to externally generated clock signal. To put the part into Standby
Mode, disable the input clock signal to this pin and pull SSON/SBM (Pin
4) low (see Table 1).
Ground Connection. Connect to system ground.
Digital logic input used to select Frequency Range (see Table 2). This pin
has an internal pull-up resistor.
Spread Spectrum On / Off and Standby Mode control (see Table 1). This
pin has an internal pull-up resistor.
2X Spread Spectrum clock output or Reference output of the input
frequency (see Table 1).
Digital logic input used to select Spreading Range (see Table 2). This pin
has an internal pull-up resistor.
Connect to +3.3V
Connect to crystal. No connect if externally generated clock signal is
used.
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
2 of 2
PRELIMINARY Specification
Alliance Semiconductor®
Figure 3 – P1812A Schematic for notebook VGA application
P1812A
1
2
Pin 4 SSON/SBM should be be
left unconnected to turn on
Spread Spectrum. Pull this pin
low to turn Spread Spectrum
OFF and enable Stand by
Mode (see note and Table 1).
CLKIN
VSS
FS0
SSON/
SBM
P1812A
P2040B
XOUT
VDD
SR0
ModOut
8
0.1uF
7
6
5
FB
VDD
3
4
20MHz-70MHz EMI reduced
clock output
Tie SR0 and FS0 High or Low according to spread
and frequency range desired (see Table 2).
External resistors are not needed to pull these pins
high.
Note:
To set the P1812A into Standby Mode, disable the input clock (CLKIN, Pin1) and also pull SSON/SBM
(Pin 4) low (see Table 1).
May, 2002
Revision C
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
3 of 3
PRELIMINARY Specification
Alliance Semiconductor®
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
, V
IN
T
STG
T
A
Parameter
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Rating
-0.5 to +7.0
-65 to +125
0 to +70
Unit
V
ºC
ºC
P1812A
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Parameter
Input Low Voltage
Input High Voltage
Input Low Current (pull-up resistor on
inputs SR0, 1)
Input High Current (pull-down resistor
on input SSON)
XOUT Output Low Current
(@ 0.4V, V
DD
= 3.3V)
XOUT Output High Current
(@ 2.5V, V
DD
= 3.3V)
Output Low Voltage
(V
DD
=3.3V, I
OL
= 20 mA)
Output High Voltage
(V
DD
=3.3V, I
OH
= 20 mA)
Static Supply Current
Standby Mode
Dynamic Supply Current
Normal Mode (3.3V and 10 pF loading)
Operating Voltage
Power Up Time
(First locked clock cycle after power up)
Clock Output Impedance
Min
GND – 0.3
2.0
-
-
-
-
-
2.5
-
TBD
f
OUT
-min
2.7
-
-
Typ
-
-
-
-
3
3
-
-
TBD
TBD
f
OUT
-typ
3.3
0.18
50
Max
0.8
V
DD
+ 0.3
-35
35
-
-
0.4
-
-
TBD
f
OUT
-max
3.7
-
-
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min
Typ
20
40
0.9
0.8
-
50
Max
35
70
1.1
1.0
360
55
Unit
MHz
MHz
ns
ns
ps
%
f
IN
Input Frequency
10
f
OUT
Spread Spectrum Output Frequency
20
t
LH
Output Rise Time
0.7
Note 1
(measured at 0.8V to 2.0V)
t
HL
Output Fall Time
0.6
Note 1
(measured at 2.0V to 0.8V)
t
JC
Jitter (cycle to cycle)
-
t
D
Output Duty Cycle
45
Note1: t
LH
and t
HL
are measured into a capacitive load of 15pF
May, 2002
Revision C
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
4 of 4
PRELIMINARY Specification
Alliance Semiconductor®
Figure 3- Mechanical Package Outline (8 Pin SOIC)
C
P1812A
L
P1812A
LOT NUMBER
YYWW
H
E
a
D
A2
A
B
e
A1
INCHES
MILLIMETERS
SYMBOL MIN
NOR MAX MIN NOR MAX
0.057 0.064 0.071 1.45 1.63 1.80
A
0.004 0.007 0.010 0.10 0.18 0.25
A1
0.053 0.061 0.069 1.35 1.55 1.75
A2
0.012 0.016 0.020 0.31 0.41 0.51
B
0.004 0.006 0.001 0.10 0.15 0.25
C
0.186 0.194 0.202 4.72 4.92 5.12
D
0.148 0.156 0.164 3.75 3.95 4.15
E
0.050 BSC
1.27 BSC
e
0.224 0.236 0.248 5.70 6.00 6.30
H
0.012 0.020 0.028 0.30 0.50 0.70
L
a
Note: Controlling dimensions are millimeters.
Figure 4 - Mechanical Package Outline (8 Pin TSSOP)
C
L
H
E
a
D
A2
A
INCHES
MILLIMETERS
SYMBOL MIN
NOR MAX MIN NOR MAX
-
-
0.047
-
-
1.10
A
0.002
-
0.006 0.05
-
0.15
A1
0.031 0.039 0.041 0.80 1.00 1.05
A2
0.007
-
0.012 0.19
-
0.30
B
0.004
-
0.008 0.09
-
0.20
C
0.114 0.118 0.122 2.90 3.00 3.10
D
0.169 0.173 0.177 4.30 4.40 4.50
E
0.026 BSC
0.65 BSC
e
0.244 0.252 0.260 6.20 6.40 6.60
H
0.018 0.024 0.030 0.45 0.60 0.75
L
-
-
a
Note: Controlling dimensions are millimeters.
Lot #
YYWW
e
A1
May, 2002
Revision C
P
1812A
B
PulseCore – A Division of Alliance Semiconductor
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
http://www.pulsecore.com
5 of 5

P1812A-08SR Related Products

P1812A-08SR P1812A-08ST
Description Clock Generator, 70MHz, CMOS, PDSO8, SOIC-8 Clock Generator, 70MHz, CMOS, PDSO8, SOIC-8
Is it Rohs certified? incompatible incompatible
Maker PulseCore Semiconductor Corporation PulseCore Semiconductor Corporation
package instruction SOIC-8 SOIC-8
Reach Compliance Code unknown unknown
JESD-30 code R-PDSO-G8 R-PDSO-G8
length 4.92 mm 4.92 mm
Number of terminals 8 8
Maximum operating temperature 70 °C 70 °C
Maximum output clock frequency 70 MHz 70 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Master clock/crystal nominal frequency 35 MHz 35 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.8 mm 1.8 mm
Maximum supply voltage 3.7 V 3.7 V
Minimum supply voltage 2.7 V 2.7 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 3.95 mm 3.95 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
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