IC61LV6432
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin LQFP and PQFP package
• 3.3V V
CC
and 2.5V V
CCQ
for I/O's
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
DESCRIPTION
The
ICSI
IC61LV6432 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
secondary cache for the Pentium™, 680X0™, and PowerPC™
microprocessors. It is organized as 65,536 words by 32 bits,
fabricated with
ICSI
's advanced CMOS technology. The
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-DQ8,
BW2
controls DQ9-DQ16,
BW3
controls DQ17-DQ24,
BW4
controls DQ25-DQ32,
conditioned by
BWE
being LOW. A LOW on
GW
input would
cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IC61LV6432 and controlled by the
ADV
(burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GND
Q
, on MODE pin selects
LINEAR Burst. A V
CCQ
(or no connect) on MODE pin selects
INTERLEAVED Burst.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
—
Parameter
CLK Access Time
Cycle Time
Frequency
-166
5
6
166
-133
5
7.5
133
-117
5
8.5
117
-5
5
10
100
-6
6
12
83
-7
7
13
75
-8
8
15
66
Unit
ns
ns
MHz
Note:
1. ADVANCE INFORMATION ONLY.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
SSR005-0A
002/02/2004
IC61LV6432
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE1
H
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE3
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
WRITE
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. "X" means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and
BWE
are LOW or
GW
is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held
HIGH throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
GW
H
H
H
X
L
BWE
H
X
L
L
X
BW1
X
H
L
L
X
BW2
X
H
H
L
X
BW3 BW4
X
H
H
L
X
X
H
H
L
X
Integrated Circuit Solution Inc.
SSR005-0A
02/02/2004
5
FPGA/CPLD
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