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UPD65977S1-XXX-B6

Description
SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256, 27 X 27 MM, PLASTIC, BGA-256
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size501KB,44 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric View All

UPD65977S1-XXX-B6 Overview

SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256, 27 X 27 MM, PLASTIC, BGA-256

UPD65977S1-XXX-B6 Parametric

Parameter NameAttribute value
MakerRenesas Electronics Corporation
Parts packaging codeBGA
package instruction27 X 27 MM, PLASTIC, BGA-256
Contacts256
Reach Compliance Codecompliant
JESD-30 codeS-PBGA-B256
length27 mm
Number of terminals256
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Maximum seat height2.2 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
width27 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR CIRCUIT

UPD65977S1-XXX-B6 Preview

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD65977S1-xxx-B6
SYSTEM-ON-CHIP LITE
GATE ARRAY WITH ARM7TDMI SUBSYSTEM
HARDWARE
DESCRIPTION
The System-on-Chip Lite ("SoCLite") is based on standard ASIC technology and consists of two blocks: an
ARM7TDMI based subsystem and a sea-of-gates area. The ARM subsystem is fully designed and verified as a
supermacro. It frees the user from the task of developing a complete RISC computer system. The sea-of-gates
area allows the user to implement custom logic or special peripheral functions.
The SoCLite is designed for embedded control applications. To maintain flexibility, SoCLite is not realized as an
ASSP (Application Specific Standard Product), this means that it can be used for a wide range of different applica-
tions. Once the customer functions are implemented into the sea-of-gates, it becomes a custom SoC.
The ARM7TDMI based subsystem of SoCLite offers a basic combination of general purpose peripheral functions,
like a serial communication interface (UART), Timer (32-bit), Interrupt Controller, Watchdog, internal RAM and
ROM (only as boot-ROM).
Functions in detail are described in the following user’s manual. Be sure to read this manual when you
design your systems.
System-on-Chip Lite User’s Manual - Hardware
: A15402EE1V0UM00
FEATURES
32-bit RISC CPU with Von Neumann Architecture
Internal 2 Kbyte ROM (boot ROM only)
Internal 8 Kbyte RAM
Serial Interface
- UART mode: 1 channel
Timer
- 32-bit timer with load register: 1 channel
- Watchdog timer: 1 channel
Interrupt Controller with 32 prioritized interrupt sources
External Bus Interface (32-bit data / 26-bit address
bus)
On-chip debug capability via JTAG
Built-in power saving mode
Power supply voltage range: 3.0 V
V
DD
3.6 V
Frequency range: up to 35 MHz for ARM subsystem
Crystal frequency range: 4 MHz
f
CRYSTAL
16 MHz
Built-in clock oscillator circuit with internal PLL
- PLL output: 6.25 MHz to 115 MHz
Temperature range: -40 °C to +85 °C
Package: 256 Plastic BGA, (27 x 27 mm)
Process: CMOS-9HD
Sea-of-Gates: 190K raw gates for user defined logic
ORDERING INFORMATION
Device
SoCLite
Part Number
µPD65977S1-xxx-B6
Package
256 PBGA
27 x 27 mm
ROM
2 K boot ROM
RAM
8K
Oper. Freq.
35 MHz
The information contained in this document is released in advance of the production cycle for the device. The parameters for the
device may change before final production, or NEC Corporation may, at its own discretion, withdraw the device prior to production.
NEC Corporation 2002
Document No. A15647EE2V0DS00
Data Published: July 2002
SoCLite
2
Preliminary Data Sheet A15647EE2V0DS00
SoCLite
INTERNAL BLOCK DIAGRAM
X1 / X2 PLLOD[1:0] EA[1:0]
User Logic
Clock
from PLL
(FCLK)
PLL
settings
JTAG
Debug
Interface
OSC
ARM7TDMI
from AHB Master
PLL
EA
Pause
AHB Bridge (AHB Master/Slave)
Arbiter
Remap
Address
Decoder
HADDR
Test mode
select
AHB
Subsystem
clock
(SCLK)
External
Memory
Interface
Address
Data
Control
TIC
(AHB Master)
E
B
I
Static Mem
Controller
(AHB Slave)
Wrapper
(AHB Slave)
ROM
2 KB
512 Words x 32
Write
Protection
Controller
(AHB Slave)
Wrapper
(AHB Slave)
Default
RAM
8 KB
2 K Words x 32
Slave
APB
Bridge
(AHB Slave)
PSEL
APB Slave
Select
APB
APB
nRST
Reset
Watchdog
(APB Slave)
Remap
Pause
(APB Slave)
UART
(APB Slave)
Timer
1 x 32 bit
(APB Slave)
Interrupt
Controller
(APB Slave)
up to 29
interrupt
sources
UDL
Reset
RxD
TxD
Preliminary Data Sheet A15647EE2V0DS00
3
SoCLite
PIN IDENTIFICATION
XADDR0 to XADDR25 : Memory Address Bus
XDATA0 to XDATA31
nXCS0 to nXCS7
nXBLS0 to nXBLS3
nXOE
nXWEN
nXWAIT
RXD
TXD
X1
X2
nRST
EA0
EA1
DBGEN
PLLOD0
PLLOD1
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
JTAG_TRST
TCLK
: Memory Data Bus
: Memory Chip (Bank) Select
: Memory Byte Lane Select
: Memory Output Enable
: Memory Read / Write
: Memory Wait
: Receive Data Input
: Transmit Data Output
: Crystal
: Crystal
: Reset
:
:
Enable signal for external
or internal boot memory
Enable signal for external
or internal boot memory
AV
DD
DV
DD
AV
SS
DV
SS
V
DD0
to V
DD11
V
SS0
to V
SS12
IC1
TEST
: Analog Power Supply for PLL
: Digital Power Supply for PLL
: Analog Ground for PLL
: Digital Ground for PLL
: Power Supply
: Ground Power Supply
: Internal connection
: Internal connection
: Debug enable
:
:
Frequency range of PLL
output
Frequency range of PLL
output
: JTAG data in
: JTAG data out
: JTAG clock
: JTAG mode select
: JTAG reset
: Clock for test purposes
4
Preliminary Data Sheet A15647EE2V0DS00
SoCLite
PIN CONFIGURATION
256-Pin Plastic BGA (27 mm
×
27 mm)
Top View
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Index mark
A B C D E F G H J K L M N P RT UVWY
Bottom View
YWVUTRPNMLKJHGFEDCBA
(1/3)
Pin
Number
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
Pin Name
V
SS0
XDATA31
XDATA29
XDATA27
nXCS2
XDATA25
XDATA24
XDATA22
XDATA20
XDATA18
XDATA17
XDATA15
XDATA14
XDATA13
XDATA12
IC1
Note1
Pin
Number
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
Pin Name
nXCS5
V
DD11
nXCS0
V
SS12
XADDR22
XADDR20
V
DD10
XADDR16
V
SS11
PLLOD0
V
DD9
IC1
Note1
V
SS10
XADDR10
XADDR9
XDATA8
Pin
Number
L1
L2
L3
L4
L17
L18
L19
L20
M1
M2
M3
M4
M17
M18
M19
M20
JTAG_TDO
JTAG_TDI
TXD
RXD
V
DD7
IC1
Note1
nXBLS1
nXBLS0
Pin Name
Pin
Number
U17
U18
U19
U20
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
Pin Name
V
SS7
Preliminary Data Sheet A15647EE2V0DS00
5
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