FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Connection Diagrams
DIP PIN CONFIGURATIONS
27C040 27C512 27C256
DIP
FM27C010
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
27C256
27C512
27C040
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
V
CC
A
18
XX/PGM
V
CC
V
CC
A
17
XX
A
14
A
14
A
14
A
14
A
13
A
13
A
13
A
13
A
8
A
8
A
8
A
8
A
9
A
9
A
9
A
9
A
11
A
11
A
11
A
11
OE
OE/V
PP
OE
OE
A
10
A
10
A
10
A
10
CE/PGM CE/PGM CE/PGM
CE
O
7
O
7
O
7
O
7
O
6
O
6
O
6
O
6
O
5
O
5
O
5
O
5
O
4
O
4
O
4
O
4
O
3
O
3
O
3
O
3
DS800032-10
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C010 pins.
Commercial Temperature Range
(0°C to +70°C) V
CC
= 5V
±10%
Parameter/Order Number
FM27C010 Q, V, 90
FM27C010 Q, V, 120
FM27C010 Q, V, 150
Package Types: FM27C010 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP package
V = PLCC package
• All packages conform to JEDEC standard.
• All versions are guaranteed to function at slower speeds.
Extended Temperature Range
(-40°C to +85°C) V
CC
= 5V
±10%
Parameter/Order Number
FM27C010 QE, VE, 90
FM27C010 QE, VE, 120
FM27C010 QE, VE, 150
Access Time (ns)
90
120
150
Access Time (ns)
90
120
150
Pin Names
A0–A16
CE
OE
O0–O7
PGM
XX
Addresses
Chip Enable
Output Enable
Outputs
Program
Don’t Care (During Read)
PLCC Pin Configuration
A
12
A
15
A
16
XX/V
PP
V
CC
XX/PGM
XX
4
3
2
1 32 31 30
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
29
28
27
26
25
24
23
22
21
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
1
O
2
GND
O
3
O
4
O
5
O
6
DS800032-3
Top View
2
FM27C010 Rev. A.1
www.fairchildsemi.com
FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages Except A9 with
Respect to Ground (Note 10)
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
-65°C to +150°C
All Output Voltages with
Respect to Ground (Note 10)
V
CC
+ 1.0V to GND - 0.6V
Operating Range
-0.6V to +7V
-0.6V to +14V
-0.6V to +7V
>2000V
Range
Commercial
Extended
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
+5V
+5V
Tolerance
±10%
±10%
DC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC
I
PP
V
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current
(CMOS)
V
CC
Standby Current (TTL)
V
CC
Active Current
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min
-0.5
2.0
Max
0.8
V
CC
+1
0.4
Units
V
V
V
V
I
OL
= 2.1 mA
I
OH
= -2.5 mA
CE = V
CC
±
0.3V
CE = V
IH
CE = OE = V
IL
I/O = 0 mA
V
PP
= V
CC
V
CC
- 0.7
V
IN
= 5.5 or GND
V
OUT
= 5.5V or GND
-1
-10
f = 5 MHz
3.5
100
1
30
10
V
CC
1
10
µA
mA
mA
µA
V
µA
µA
AC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output
Float
Output Hold from
Addresses, CE or OE ,
Whichever Occurred First
0
90
Max
90
90
40
35
120
Min
Max
120
120
50
35
150
Min
Max
150
150
50
45
Units
ns
0
0
Capacitance
T
A
= +25°C, f = 1 MHz (Note 2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
6
10
Max
15
15
Units
pF
pF
3
FM27C010 Rev. A.1
www.fairchildsemi.com
FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
≤5
ns
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs
AC Waveforms
(Note 6), (Note 7), and (Note 9)
ADDRESS
2V
0.8V
Address Valid
CE
2V
0.8V
t
CF
(Note 4, 5)
OE
0.8V
t
OE
(Note 3)
2V
0.8V
2V
t
CE
t
DF
(Note 4, 5)
Valid Output
OUTPUT
Hi-Z
t
ACC
(Note 3)
Hi-Z
t
OH
DS800032-4
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE.
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
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