HN29W51214S Series
512M AND type Flash Memory
More than 16,057-sector (271,299,072-bit)
×
2
ADE-203-1155 (Z)
Preliminary
Rev. 0.0
Jan. 24, 2000
Description
The Hitachi HN29W51214S Series is stacked 2 chips Hitachi 256-Mbit Flash memory (HN29W25611S) that
are CMOS Flash Memory with AND type memory cells. It has fully automatic programming and erase
capabilities with a single 3.3 V power supply. The functions are compatible with HN29W25611S Series and
controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase
is as small as (2048 + 64) bytes. Initial available sectors of HN29W51214S are more than 32,114 (98% of all
sector address).
Features
•
On-board single power supply (V
CC
): V
CC
= 3.3 V
±
0.3 V
•
Organization
AND Flash Memory: (2048 + 64) bytes
×
(More than 16,057 sectors)
×
2
Data register: (2048 + 64) bytes
×
2
•
Multi-level memory cell
2 bit/per memory cell
•
Automatic programming
Sector program time: 3.0 ms (typ)
System bus free
Address, data latch function
Internal automatic program verify function
Status data polling function
•
Automatic erase
Single sector erase time: 1.5 ms (typ)
System bus free
Internal automatic erase verify function
Status data polling function
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
HN29W51214S Series
•
Erase mode
Single sector erase ((2048 + 64) byte unit)
•
Fast serial read access time:
First access time: 50 µs (max)
Serial access time: 50/80 ns (max)
•
Low power dissipation:
I
CC2
= 100 mA (max) (Read)
I
SB2
= 100 µA (max) (Standby)
I
CC3
/I
CC4
= 80 mA (max) (Erase/Program)
I
SB3
= 10 µA (max) (Deep standby)
•
The following architecture is required for data reliability.
Error correction: more than 3-bit error correction per each sector read
Spare sectors: 1.8% (290 sectors) within usable sectors
Ordering Information
Type No.
HN29W51214ST-50
HN29W51214ST-80
Available sector
More than 32,114 sectors
Package
12.0
×
18.40 mm
2
0.5 mm pitch
48-pin plastic TSOP I (TFP-48DA)
2
HN29W51214S Series
Pin Arrangement
48-pin TSOP
V
CC
*
4
V
SS1
*
4
V
SS1
*
4
V
SS1
*
4
V
SS1
*
4
RES*
4
RDY/Busy*
4
SC*
4
OE*
4
I/O0*
4
I/O1*
4
I/O2*
4
I/O3*
4
TEST1*
1, 4
TEST2*
2, 4
I/O4*
4
I/O5*
4
I/O6*
4
I/O7*
4
CDE*
4
WE*
4
CE*
4
TEST3*
3, 4
V
SS2
*
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Top view)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
*
5
V
SS1
*
5
V
SS1
*
5
V
SS1
*
5
V
SS1
*
5
RES*
5
RDY/Busy*
5
SC*
5
OE*
5
I/O0*
5
I/O1*
5
I/O2*
5
I/O3*
5
TEST1*
1, 5
TEST2*
2, 5
I/O4*
5
I/O5*
5
I/O6*
5
I/O7*
5
CDE*
5
WE*
5
CE*
5
TEST3*
3, 5
V
SS2
*
5
Notes: 1.
2.
3.
4.
5.
TEST1 pin should be connected to a power supply (V
CC
).
TEST2 pin should be connected to a ground (V
SS
).
TEST3 pin should be connected to a ground (V
SS
).
Upper chip.
Lower chip.
3
HN29W51214S Series
Pin Description
Pin name
I/O0 to I/O7
CE
OE
WE
CDE
V
CC
*
1
V
SS1
to V
SS2
*
1
RDY/Busy
RES
SC
TEST1 to TEST3
Note:
Function
Input/output
Chip enable
Output enable
Write enable
Command data enable
Power supply
Ground
Ready/Busy
Reset
Serial clock
Test pin
1. All V
CC
and V
SS
pins should be connected to a common power supply and a ground, respectively.
4
HN29W51214S Series
Block Diagram
Upper pellet
2048 + 64
X-decoder
16384
×
(512 + 64)
×
8
memory matrix
••
I/O0
to
I/O7
Data
input
buffer
Input
data
control
Data register (2048 + 64)
•
•
•
Multiplexer •
•
•
•
•
Y-gating
Y-decoder
Data
output
buffer
•••
RDY/Busy
••
Y-address
counter
V
CC
V
SS
CE
OE
WE
SC
RES
CDE
Control
signal
buffer
Read/Program/Erase control
Lower pellet
2048 + 64
X-decoder
16384
×
(2048 + 64)
×
8
memory matrix
••
I/O0
to
I/O7
Data
input
buffer
Input
data
control
Data register (2048 + 64)
•
•
•
Multiplexer •
•
•
•
•
Y-gating
Y-decoder
Data
output
buffer
•••
RDY/Busy
••
Y-address
counter
V
CC
V
SS
CE
OE
WE
SC
RES
CDE
Control
signal
buffer
Read/Program/Erase control
16057 - 16384
Sector
address
buffer
16057 - 16384
Sector
address
buffer
5
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