HT95AXXX
I/O Type Phone 8-Bit MCU
Features
·
Provide MASK type and OTP type version
·
Operating voltage range: 2.4V~5.5V
·
Program ROM
-
HT95A400/40P: 16K´16 bits
-
HT95A300/30P: 8K´16 bits
-
HT95A200/20P: 4K´16 bits
-
HT95A100/10P: 4K´16 bits
·
Data RAM
-
HT95A400/40P: 2880´8 bits
-
HT95A300/30P: 2112´8 bits
-
HT95A200/20P: 1152´8 bits
-
HT95A100/10P: 384´8 bits
·
Bidirectional I/O lines
-
HT95A400/40P: 44
-
HT95A300/30P: 28
-
HT95A200/20P: 28
-
HT95A100/10P: 20
·
Timer
-
Two 16-bit programmable Timer/Event Counter
-
Real time clock (RTC)
-
Watchdog Timer (WDT)
·
Programmable frequency divider (PFD)
Supported for HT95A400/40P, HT95A300/30P,
HT95A200/20P
·
Dual system clock: 32768Hz, 3.58MHz
·
Four operating modes: Idle mode, Sleep mode,
Green mode and Normal mode
·
Up to 1.117ms instruction cycle with 3.58MHz system
clock
·
All instructions in one or two machine cycles
·
Built-in 3.58MHz DTMF Generator
·
Built-in dialer I/O
·
HT95A400/40P: 64-pin LQFP package
I/O lines
I/O lines
I/O lines
I/O lines
·
16-bit table read instructions
·
Subroutine nesting
-
HT95A400/40P: 12 levels
-
HT95A300/30P: 8 levels
-
HT95A200/20P: 8 levels
-
HT95A100/10P: 4 levels
HT95A300/40P: 48-pin SSOP package
HT95A200/20P: 48-pin SSOP package
HT95A100/10P: 28-pin SOP package
Applications
·
Cordless Phone
·
Fax and answering machines
·
Other communication system
General Description
The HT95AXXX family MCU are 8-bit high performance
RISC-like microcontrollers with built-in DTMF generator
and dialer I/O which provide MCU dialer implementation
or system control features for telecom product applica-
tions. The phone controller has a built-in program ROM,
data RAM and I/O lines for high end products design. In
addition, for power management purpose, it has a
built-in frequency up conversion circuit (32768Hz to
3.58MHz) which provides dual system clock and four
types of operation modes. For example, it can operate
with low speed system clock rate of 32768Hz in green
mode with little power consumption. It can also operate
with high speed system clock rate of 3.58MHz in normal
mode for high performance operation. To ensure
smooth dialer function and to avoid MCU shut-down in
extreme low voltage situation, the dialer I/O circuit is
built-in to generate hardware dialer signals such as
on-hook, hold-line and hand-free. Built-in real time clock
and programmable frequency divider are provided for
additional fancy features in product developments. The
device is best suited for phone products that comply
with versatile dialer specification requirements of differ-
ent areas or countries.
Rev. 1.51
1
February 20, 2009
HT95AXXX
Selection Table
Part No.
HT95A100
HT95A10P
HT95A200
HT95A20P
HT95A300
HT95A30P
HT95A400
HT95A40P
HT95L000
HT95L00P
HT95L100
HT95L10P
HT95L200
HT95L20P
HT95L300
HT95L30P
HT95L400
HT95L40P
HT95C200
HT95C20P
HT95C300
HT95C30P
HT95C400
HT95C40P
Operating Program
Data
Normal Dialer
Voltage
Memory Memory
I/O
I/O
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
2.4V~5.5V
4K´16
4K´16
8K´16
16K´16
4K´16
4K´16
8K´16
8K´16
16K´16
8K´16
8K´16
16K´16
384´8
1152´8
2112´8
2880´8
384´8
1152´8
1152´8
2112´8
2880´8
1152´8
2112´8
2880´8
20
28
28
44
14~18
16~20
20~28
16~28
28~40
20~28
16~28
28~40
6
8
8
8
6
8
8
8
8
8
8
8
LCD
¾
¾
¾
¾
12´8~16´8
16´8~20´8
24´8~24´16
36´16~48´16
36´16~48´16
24´8~24´16
36´16~48´16
36´16~48´16
Timer
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
16-bit´2
Stack
4
8
8
12
4
8
8
8
12
8
8
12
External
Interrupt
3
4
4
4
3
4
4
4
4
4
4
4
DTMF
Generator
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
FSK
Receiver
¾
¾
¾
¾
¾
¾
¾
¾
¾
Ö
Ö
Ö
Package
28SOP
48SSOP
48SSOP
64LQFP
56SSOP
64LQFP
100QFP
100QFP
128QFP
128QFP
128QFP
128QFP
Note: Part numbers suffixed with
²P²
are OTP devices, all others are mask version devices.
Block Diagram (HT95A400/40P)
R E S
P o w e r D o w n
D e te c to r &
R e s e t C ir c u it
P ro g ra m
C o u n te r
P ro g ra m
R O M
S T A C K 0
S T A C K 1
S T A C K 2
3 2 7 6 8 H z
In te rru p t
C ir c u it
R T C
IN T C 0
IN T C 1
T M R 1
T M R 1 C
M
U
X
3 2 7 6 8 H z
IN T
T M R 1
S T A C K 9
S T A C K 1 0
S T A C K 1 1
In s tr u c tio n
R e g is te r
M P 0
M P 1
M
T M R 0
T M R 0 C
U
X
D A T A
M e m o ry
P A
P A C
M
U
T M R 0
X
c lo c k /4
S y s te m
P A 0 ~ P A 7
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
A C C
M U X
P B
P B C
P D
P D C
P E
P E C
P F
P F C
P G
P G C
P B 0 ~ P B 7
S T A T U S
P D 0 ~ P D 7
S h ifte r
P E 0 ~ P E 7
X 1
X 2
X C
H F I
H F O
H D I
H D O
H K S
P O
D N P O
X M U T E
V D D
V S S
P F 0 ~ P F 7
O S C
C ir c u it
3 2 7 6 8 H z
W D T O S C
S y s te m C lo c k /4
M
W D T S
U
X
W D T P r e s c a le r
P G 0 ~ P G 3
D ia le r I/O
D T M F
G e n e ra to r
3 .5 8 M H z
3 2 7 6 8 H z
o r 3 .5 8 M H z /4
P F D
D T M F
P o w e r
S u p p ly
M U S IC
Rev. 1.51
2
February 20, 2009
HT95AXXX
Pin Assignment
P A 3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
P A 2
P A 1
P A 0
P B 7
P B 6
P B 5
P B 4
V S S
P B 3
P A 3
P A 2
P A 1
P A 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
V S S
D N P O
9
1 0
1 1
1 2
1 3
1 4
8
7
6
5
4
3
2
1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
P A 4
P A 5
P A 6
P A 7
D T M F
P D 0
P D 1
X 2
X 1
X C
V D D
R E S
IN T /T M R 0
X M U T E
P B 2
P B 1
P B 0
P D 7
P D 6
P D 5
P D 4
P D 3
P D 2
P D 1
P D 0
IN T
T M R 0
T M R 1
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
P A 4
P A 5
P A 6
P A 7
X 2
X 1
X C
N C
V D D
R E S
D T M F
H F I
H F O
H D I
H D O
X M U T E
D N P O
P O
H K S
P E 3
P E 2
P E 1
P E 0
M U S IC
P G
P A
P A
P A
P A
P A
P A
P A
P A
P B
P B
P B
P B
P B
P B
P B
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
9
8
1 0
1 1
1 2
1 3
1 4
1 5
1 6
7
H T 9 5 A 4 0 0 /4 0 P
6 4 L Q F P -A
6
5
3
4
0
1
2
P E 3
P E 2
P E 1
P E 0
P F 7
P F 6
P F 5
P F 4
P F 3
P F 2
P F 1
P F 0
N C
P G 3
P G 2
P G 1
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 4 5 3 5 2
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
P E 4
P E 5
P E 6
P E 7
P D 0
P D 1
P D 2
P D 3
P D 4
P D 5
P D 6
P D 7
M U S IC
R E S
T M R 0
D T M F
T M R 1
X C
X 2
X 1
IN T
V D D
V S S
H F I
H F O
H D I
H D O
H K S
P O
D N P O
X M U T E
P B 0
H T 9 5 A 1 0 0 /1 0 P *
2 8 S O P -A
H T 9 5 A 3 0 0 /3 0 P /2 0 0 /2 0 P
4 8 S S O P -A
Note:
²*²
The following pads for the HT95A100/10P are not bonded to the package.
PD2, PD3, HKS, PO, HFI, HFO
Pin Description
Pin Name
CPU
VDD
VSS
X1
X2
XC
RES
¾
¾
I
O
I
I
Positive power supply
Negative power supply, ground
A 32768Hz crystal (or resonator) should be connected to this pin and X2.
A 32768Hz crystal (or resonator) should be connected to this pin and X1.
External low pass filter used for frequency up conversion circuit.
Schmitt trigger reset input, active low.
Supported for HT95A400/40P, HT95A300/30P, HT95A200/20P
Schmitt trigger input for external interrupt.
No internal pull-high resistor.
Edge trigger activated on a falling edge.
Supported for HT95A400/40P, HT95A300/30P, HT95A200/20P
Schmitt trigger input for Timer/Event Counter 0.
No internal pull-high resistor.
Activated on falling or rising transition edge, selected by software.
Activated on a falling or rising transition edge, selected by software.
Supported for HT95A100/10P
Schmitt trigger input for external interrupt or Timer/Event Counter 0.
No internal pull-high resistor.
For INT: Edge trigger activated on a falling edge.
For TMR0: Activated on a falling or rising transition edge, selected by software.
Supported for HT95A400/40P, HT95A300/30P, HT95A200/20P
Schmitt trigger input for Timer/Event Counter 1.
No internal pull-high resistor.
Activated on falling or rising transition edge, selected by software.
I/O
Description
INT
I
TMR0
I
INT/TMR0
I
TMR1
I
Rev. 1.51
3
February 20, 2009
HT95AXXX
Pin Name
Normal I/O
PA7~PA0
I/O
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high and wake-up function.
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
Schmitt trigger input structure. An external RC network is recommended for input
debouncing.
This pin is pulled low with internal resistance of 200kW typ.
CMOS output structure.
Schmitt trigger input structure. An external RC network is recommended for input
debouncing.
This pin is pulled high with internal resistance of 200kW typ.
CMOS output structure.
This pin detects the status of the hook-switch and its combination with HFI/HDI can con-
trol the PO pin output to make or break the line.
CMOS output structure controlled by HKS and HFI/HDI pins and which determines
whether the dialer connects or disconnects the telephone line.
NMOS output structure.
NMOS output structure. Usually, XMUTE is used to mute the speech circuit when trans-
mitting the dialer signal.
This pin outputs dual tone signals to dial out the phone number. The load resistor should
not be less than 5kW.
This pin outputs the single tone that is generated by the PFD generator.
I/O
Description
PB7~PB0
I/O
PD7~PD0
I/O
PE7~PE0
I/O
PF7~PF0
I/O
PG3~PG0
I/O
Dialer I/O (See the
²Dialer
I/O Function²)
HFI
HFO
HDI
HDO
HKS
PO
DNPO
XMUTE
Peripherals
DTMF
MUSIC
O
O
I
O
I
O
I
O
O
O
Absolute Maximum Ratings
Supply Voltage ..........................V
SS
-0.3V
to V
SS
+5.5V
Input Voltage .............................. V
SS
-0.3
to V
DD
+0.3V
Storage Temperature ...........................-50°C to 125°C
Operating Temperature ..........................-20°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 1.51
4
February 20, 2009
HT95AXXX
Electrical Characteristics
Symbol
CPU
I
IDL
I
SLP
I
GRN
Idle Mode Current
Sleep Mode Current
Green Mode Current
5V
5V
5V
32768Hz off, 3.58MHz off,
CPU off, WDT off, no load
32768Hz on, 3.58MHz off,
CPU off, WDT off, no load
32768Hz on, 3.58MHz off,
CPU on, WDT off, no load
32768Hz on, 3.58MHz on,
CPU on, WDT on,
DTMF generator off, no load
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
4
4
-2
10
¾
17
28
2
30
50
mA
mA
mA
Parameter
Test Conditions
V
DD
Conditions
Min.
Typ.
Max.
Ta=25°C
Unit
I
NOR
V
IL
V
IH
I
OL
I
OH
R
PH
Dialer I/O
I
XMO
I
OLXM
I
HKS
R
HFI
R
HDI
I
OH2
I
OL2
I
OH3
I
OL3
I
OH4
I
OL4
I
OL5
Normal Mode Current
I/O Port Input Low Voltage
I/O Port Input High Voltage
I/O Port Sink Current
I/O Port Source Current
Pull-high Resistor
5V
5V
5V
5V
5V
5V
1.8
¾
¾
6
-3
30
3
1
5
¾
¾
¾
mA
V
V
mA
mA
kW
XMUTE Leakage Current
XMUTE Sink Current
HKS Input Current
HFI Pull-low Resistance
HDI Pull-high Resistance
HFO Source Current
HFO Sink Current
HDO Source Current
HDO Sink Current
PO Source Current
PO Sink Current
DNPO Sink Current
2.5V XMUTE pin=2.5V
2.5V XMUTE pin=0.5V
2.5V HKS pin=2.5V
2.5V V
HFI
=2.5V
2.5V V
HDI
=0V
2.5V V
OH
=2V
2.5V V
OL
=0.5V
2.5V V
OH
=2V
2.5V V
OL
=0.5V
2.5V V
OH
=2V
2.5V V
OL
=0.5V
2.5V V
OL
=0.5V
¾
1
¾
¾
¾
-1
1
-1
1
-1
1
1
¾
¾
¾
200
200
¾
¾
¾
¾
¾
¾
¾
1
¾
0.1
¾
¾
¾
¾
¾
¾
¾
¾
¾
mA
mA
mA
kW
kW
mA
mA
mA
mA
mA
mA
mA
DTMF Generator
V
TDC
V
TOL
V
TAC
R
L
A
CR
THD
DTMF Output DC Level
DTMF Sink Current
DTMF Output AC Level
DTMF Output Load
Column Pre-emphasis
Tone Signal Distortion
¾
¾
¾
¾
¾
¾
V
DTMF
=0.5V
Row group, R
L
=5kW
THD£-23dB
Row group=0dB
R
L
=5kW
¾
0.45V
DD
0.1
120
5
1
¾
¾
¾
155
¾
2
-30
0.7V
DD
¾
180
¾
3
-23
V
mA
mVrms
kW
dB
dB
Rev. 1.51
5
February 20, 2009
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