XCV600E-8HQ240C datasheet, PDF

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XCV600E-8HQ240C: DescriptionFPGA, 3456 CLBS, 186624 GATES, 416MHz, PQFP240, HQFP-240; CategoryProgrammable logic devices Programmable logic; File Size1MB，55 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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XCV600E-8HQ240C Overview

FPGA, 3456 CLBS, 186624 GATES, 416MHz, PQFP240, HQFP-240

XCV600E-8HQ240C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	QFP
package instruction	FQFP,
Contacts	240
Reach Compliance Code	unknown
maximum clock frequency	416 MHz
Combined latency of CLB-Max	0.4 ns
JESD-30 code	S-PQFP-G240
JESD-609 code	e0
length	32 mm
Humidity sensitivity level	3
Configurable number of logic blocks	3456
Equivalent number of gates	186624
Number of terminals	240
Maximum operating temperature	85 °C
Minimum operating temperature
organize	3456 CLBS, 186624 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	COMMERCIAL
Maximum seat height	4.1 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	32 mm

XCV600E-8HQ240C Preview

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Virtex™-E 1.8 V

Field Programmable Gate Arrays

DS022-2 (v2.8) January 16, 2006

Production Product Specification

Architectural Description

Virtex-E Array

The Virtex-E user-programmable gate array, shown in

Figure 1,

comprises two major configurable elements: con-

figurable logic blocks (CLBs) and input/output blocks (IOBs).

•

CLBs provide the functional elements for constructing

logic

IOBs provide the interface between the package pins

and the CLBs

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

Input/Output Block

The Virtex-E IOB,

Figure 2,

features SelectI/O+ inputs and

outputs that support a wide variety of I/O signalling stan-

dards, see

Table 1.

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

TCE

D Q

Weak

Keeper

DLLDLL

OCE

D Q

PAD

OBUFT

VersaRing

Programmable

Delay

IBUF

BRAMs

CLBs

IOBs

Vref

CLK

ICE

ds022_02_091300

IOBs

Figure 2:

Virtex-E Input/Output Block (IOB)

VersaRing

DLLDLL

ds022_01_121099

Figure 1:

Virtex-E Architecture Overview

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

The Virtex-E architecture also includes the following circuits

that connect to the GRM.

•

Dedicated block memories of 4096 bits each

Clock DLLs for clock-distribution delay compensation

and clock domain control

3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing

resources

The three IOB storage elements function either as

edge-triggered D-type flip-flops or as level-sensitive latches.

Each IOB has a clock signal (CLK) shared by the three

flip-flops and independent clock enable signals for each

flip-flop.

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-2 (v2.8) January 16, 2006

Production Product Specification

www.xilinx.com

Module 2 of 4

Virtex™-E 1.8 V Field Programmable Gate Arrays

Table 1:

Supported I/O Standards

I/O

Standard

LVTTL

LVCMOS2

LVCMOS18

SSTL3 I & II

SSTL2 I & II

GTL

GTL+

HSTL I

HSTL III & IV

CTT

AGP-2X

PCI33_3

PCI66_3

BLVDS & LVDS

LVPECL

Output

CCO

3.3

2.5

1.8

3.3

2.5

N/A

1.5

3.3

2.5

3.3

Input

CCO

3.3

2.5

1.8

N/A

3.3

N/A

Input

REF

N/A

1.50

1.25

0.80

1.0

0.75

0.90

1.50

1.32

N/A

Board

Termination

Voltage (V

)

N/A

1.50

1.25

1.20

1.50

0.75

1.50

N/A

Input Path

The Virtex-E IOB input path routes the input signal directly

to internal logic and/ or through an optional input flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold voltage, V

REF

. The need to supply V

REF

imposes

constraints on which standards can be used in close prox-

imity to each other. See

I/O Banking.

There are optional pull-up and pull-down resistors at each

user I/O input for use after configuration. Their value is in

the range 50 – 100 kΩ.

Output Path

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48 mA. Drive

strength and slew rate controls minimize bus transients.

In most signalling standards, the output High voltage

depends on an externally supplied V

CCO

voltage. The need

to supply V

CCO

imposes constraints on which standards

can be used in close proximity to each other. See

I/O Bank-

ing.

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

Since the weak-keeper circuit uses the IOB input buffer to

monitor the input level, an appropriate V

REF

voltage must be

provided if the signalling standard requires one. The provi-

sion of this voltage must comply with the I/O banking rules.

In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). For each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

The output buffer and all of the IOB control signals have

independent polarity controls.

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. After

configuration, clamping diodes are connected to V

CCO

with

the exception of LVCMOS18, LVCMOS25, GTL, GTL+,

LVDS, and LVPECL.

Optional pull-up, pull-down and weak-keeper circuits are

attached to each pad. Prior to configuration all outputs not

involved in configuration are forced into their high-imped-

ance state. The pull-down resistors and the weak-keeper

circuits are inactive, but I/Os can optionally be pulled up.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins are in a

high-impedance state. Consequently, external pull-up or

pull-down resistors must be provided on pins required to be

at a well-defined logic level prior to configuration.

All Virtex-E IOBs support IEEE 1149.1-compatible Bound-

ary Scan testing.

I/O Banking

Some of the I/O standards described above require V

CCO

and/or V

REF

voltages. These voltages are externally sup-

plied and connected to device pins that serve groups of

IOBs, called banks. Consequently, restrictions exist about

which I/O standards can be combined within a given bank.

Module 2 of 4

www.xilinx.com

DS022-2 (v2.8) January 16, 2006

Production Product Specification

Virtex™-E 1.8 V Field Programmable Gate Arrays

In Virtex-E, input buffers with LVTTL, LVCMOS2,

LVCMOS18, PCI33_3, PCI66_3 standards are supplied by

CCO

rather than V

CCINT

. For these standards, only input

and output buffers that have the same V

CCO

can be mixed

together.

The V

CCO

and V

REF

pins for each bank appear in the device

pin-out tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

Within a given package, the number of V

REF

and V

CCO

pins

can vary depending on the size of device. In larger devices,

more I/O pins convert to V

REF

pins. Since these are always

a super set of the V

REF

pins used for smaller devices, it is

possible to design a PCB that permits migration to a larger

device if necessary. All the V

REF

pins for the largest device

anticipated must be connected to the V

REF

voltage, and not

used for I/O.

In smaller devices, some V

CCO

pins used in larger devices

do not connect within the package. These unconnected pins

can be left unconnected externally, or can be connected to

the V

CCO

voltage to permit migration to a larger device if

necessary.

Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in

Figure 3.

Each bank has

multiple V

CCO

pins, all of which must be connected to the

same voltage. This voltage is determined by the output

standards in use.

Bank 0

Bank 7

Bank 1

Bank 2

ds022_03_121799

GCLK3 GCLK2

VirtexE

Device

Bank 6

GCLK1 GCLK0

Bank 5

Bank 4

Bank 3

Figure 3:

Virtex-E I/O Banks

Within a bank, output standards can be mixed only if they

use the same V

CCO

. Compatible standards are shown in

Table 2.

GTL and GTL+ appear under all voltages because

their open-drain outputs do not depend on V

CCO

Table 2:

Compatible Output Standards

CCO

3.3 V

2.5 V

1.8 V

1.5 V

Compatible Standards

PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+, LVPECL

SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,

BLVDS, LVDS

LVCMOS18, GTL, GTL+

HSTL I, HSTL III, HSTL IV, GTL, GTL+

Configurable Logic Blocks

The basic building block of the Virtex-E CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The output from the function

generator in each LC drives both the CLB output and the D

input of the flip-flop. Each Virtex-E CLB contains four LCs,

organized in two similar slices, as shown in

Figure 4.

Figure 5

shows a more detailed view of a single slice.

In addition to the four basic LCs, the Virtex-E CLB contains

logic that combines function generators to provide functions

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

Look-Up Tables

Some input standards require a user-supplied threshold

voltage, V

REF

. In this case, certain user-I/O pins are auto-

matically configured as inputs for the V

REF

voltage. Approx-

imately one in six of the I/O pins in the bank assume this

role.

The V

REF

pins within a bank are interconnected internally

and consequently only one V

REF

voltage can be used within

each bank. All V

REF

pins in the bank, however, must be con-

nected to the external voltage source for correct operation.

Within a bank, inputs that require V

REF

can be mixed with

those that do not. However, only one V

REF

voltage can be

used within a bank.

Virtex-E function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16 x 1-bit dual-port synchronous RAM.

The Virtex-E LUT can also provide a 16-bit shift register that

is ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

DS022-2 (v2.8) January 16, 2006

Production Product Specification

www.xilinx.com

Module 2 of 4

Virtex™-E 1.8 V Field Programmable Gate Arrays

COUT

LUT

Carry &

Control

D Q

LUT

Carry &

Control

D Q

LUT

Slice 0

Carry &

Control

D Q

LUT

Carry &

Control

D Q

Slice 1

CIN

ds022_04_121799

Figure 4:

2-Slice Virtex-E CLB

COUT

LUT

INIT

D Q

REV

F5IN

LUT

CLK

REV

WSO

WSH

BY DG

INIT

CIN

ds022_05_092000

Figure 5:

Detailed View of Virtex-E Slice

Storage Elements

The storage elements in the Virtex-E slice can be config-

ured either as edge-triggered D-type flip-flops or as

level-sensitive latches. The D inputs can be driven either by

the function generators within the slice or directly from slice

inputs, bypassing the function generators.

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

Module 2 of 4

www.xilinx.com

DS022-2 (v2.8) January 16, 2006

Production Product Specification

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XCV600E-8HQ240C Related Products

	XCV600E-8HQ240C	XCV1000E-6HQ240C	XCV2000E-6FG860I	XCV1000E-8HQ240C
Description	FPGA, 3456 CLBS, 186624 GATES, 416MHz, PQFP240, HQFP-240	FPGA, 6144 CLBS, 331776 GATES, 357MHz, PQFP240, HQFP-240	FPGA, 9600 CLBS, 518400 GATES, 357MHz, PBGA860, FBGA-860	FPGA, 6144 CLBS, 331776 GATES, 416MHz, PQFP240, HQFP-240
Is it lead-free?	Contains lead	Lead free	Contains lead	Contains lead
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
Parts packaging code	QFP	QFP	BGA	QFP
package instruction	FQFP,	FQFP,	FBGA-860	FQFP,
Contacts	240	240	860	240
Reach Compliance Code	unknown	unknown	unknown	unknow
maximum clock frequency	416 MHz	357 MHz	357 MHz	416 MHz
Combined latency of CLB-Max	0.4 ns	0.47 ns	0.47 ns	0.4 ns
JESD-30 code	S-PQFP-G240	S-PQFP-G240	S-PBGA-B860	S-PQFP-G240
JESD-609 code	e0	e0	e0	e0
length	32 mm	32 mm	42.5 mm	32 mm
Humidity sensitivity level	3	3	3	3
Configurable number of logic blocks	3456	6144	9600	6144
Equivalent number of gates	186624	331776	518400	331776
Number of terminals	240	240	860	240
organize	3456 CLBS, 186624 GATES	6144 CLBS, 331776 GATES	9600 CLBS, 518400 GATES	6144 CLBS, 331776 GATES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	FQFP	BGA	FQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	GRID ARRAY	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	225	225	225	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Maximum seat height	4.1 mm	4.1 mm	2.2 mm	4.1 mm
Maximum supply voltage	1.89 V	1.89 V	1.89 V	1.89 V
Minimum supply voltage	1.71 V	1.71 V	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	GULL WING	GULL WING	BALL	GULL WING
Terminal pitch	0.5 mm	0.5 mm	1 mm	0.5 mm
Terminal location	QUAD	QUAD	BOTTOM	QUAD
Maximum time at peak reflow temperature	30	30	30	30
width	32 mm	32 mm	42.5 mm	32 mm
Is it Rohs certified?	incompatible	incompatible	-	incompatible
Maximum operating temperature	85 °C	85 °C	-	85 °C
Temperature level	OTHER	OTHER	-	OTHER

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