Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
CONTENTS
1
2
2.1
3
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
8.1
8.2
8.3
9
10
10.1
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
FEATURES
DESCRIPTION
Compatibility between P90CL301AFH and
P90CL301BFH
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
Pinning
Pin description
SYSTEM CONTROL
Memory organization
Programmable chip-select
Dynamic bus port sizing
System Control Register (SYSCON)
Reset operation
Clock generation
Interrupt controller
Power reduction modes
CPU FUNCTIONAL DESCRIPTION
General
Programming model and data organization
Processing states and exception processing
Tracing
Stack format
CPU interrupt processing
Bus arbitration
PORTS
Port P Control Register (PCON)
Port SP
Ports schematics
8051 PERIPHERAL BUS
ON-CHIP PERIPHERAL FUNCTIONS
Peripheral interrupt control
TIMERS
Timer array
Timebase
Channel function
Pin parallel functions for the timer
Timer Control Registers
Timer Status Register
Watchdog Timer
13.1
13.2
14
14.1
15
15.1
15.2
16
17
18
19
20
21
22
23
24
25
26
26.1
27
28
29
29.1
29.2
29.3
29.4
30
31
32
12
12.1
12.2
12.3
12.4
12.5
13
P90CL301BFH (C100)
SERIAL INTERFACES
UART interface
Baud rate generator
UART queue
I
2
C-bus interface
Serial Control Register (SCON)
PULSE WIDTH MODULATION OUTPUTS
(PWM)
Prescaler PWM Register (PWMP)
PWM Data Registers (PWM0 and PWM1)
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADC Control Register (ADCON)
ON-BOARD TEST CONCEPT
ONCE mode
Test ROM
ON-CHIP RAM
REGISTER MAPPING
LIMITING VALUES
DC CHARACTERISTICS
ADC CHARACTERISTICS
AC CHARACTERISTICS
8051 BUS TIMING
TIMING DIAGRAMS
CLOCK TIMING
PIN STATES IN VARIOUS MODES
INSTRUCTION SET AND ADDRESSING
MODES
Addressing modes
INSTRUCTION TIMING
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
1996 Dec 11
2
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
1
FEATURES
P90CL301BFH (C100)
•
512 bytes RAM on-chip
•
On-Circuit Emulation (ONCE) mode and internal
Test-ROM (256 bytes) for on-board testing
•
80-pin LQFP package
•
Temperature range
−40
to +85
°C
•
0.5 micron CMOS low voltage technology.
2
DESCRIPTION
•
Fully 68000 software compatible
•
Static design with 32-bit internal structure
•
Power saving modes: Power-down, Standby and Idle
mode
•
External clock input: 27 MHz at 2.7 V
•
Single supply voltage of 2.7 to 3.6 V; down to 1.8 V for
RAM retention
•
68000 compatible bus interface
•
Intel 8051 compatible bus interface
•
16 Mbytes program/data address range
•
8 programmable chip-selects
•
Dynamic bus sizing, 16 or 8-bit memory bus port size
•
56 powerful instruction types:
– 5 basic data types, and
– 14 addressing modes
•
7 programmable interrupt inputs:
– a Non-Maskable Interrupt input (NMIN)
– 14 auto-vectored interrupts and 7 interrupt priority
levels
•
24 port pins (multiplexed with other functions)
•
2 UART serial interfaces; an independent baud rate
generator with two programmable outputs (UART0 and
UART1)
•
UART queue with maximum 256 bytes
•
I
2
C-bus serial interface 100 kbaud
•
2 timer arrays including:
– two 16-bit reference counters and 8-bit
programmable prescalers
– six 16-bit match/capture registers with equality
comparators
•
Watchdog Timer with 21-bit resolution
•
Two 8-bit Pulse Width Modulation (PWM) outputs with
8-bit prescaler
•
Four 8-bit Analog-to-Digital Converter (ADC) inputs with
Power-down mode
3
ORDERING INFORMATION
The P90CL301BFH is a highly integrated low-voltage
16/32-bit microcontroller especially suitable for digital
mobile systems such as GSM, DCS1900, IS54/95 and
other applications requiring low voltage, low power
consumption and high computing power. It is fully software
compatible with the 68000.
The P90CL301BFH optimizes system cost by providing
both standard as well as advanced peripheral functions
on-chip. The P90CL301BFH has a full static design and
special Idle, Standby and Power-down modes which allow
further reduction of the total system power consumption.
An 80-pin LQFP package dramatically reduces system
size requirements.
2.1
Compatibility between P90CL301AFH and
P90CL301BFH
For functional compatibility between P90CL301AFH
(SAC1 process) and P90CL301BFH (C100 process), the
following points should be considered when using the
P90CL301BFH:
•
Wake-up;
to wake-up the processor from Power-down
mode via the activation of an external SPn pin, it is
necessary to enable the interrupt mode first by setting
the corresponding bit in the SPCON register.
•
SYSCON register;
for the P90CL301AFH bits 11 to 15
in the SYSCON register should not be set in order to
keep additional functionality in the P90CL301BFH
inactive.
PACKAGE
TYPE NUMBER
NAME
P90CL301BFH
LQFP80
DESCRIPTION
plastic low profile quad flat package; 80 leads;
body 12
×
12
×
1.4 mm
3
VERSION
SOT315-1
TEMPERATURE
RANGE (°C)
−40
to +85
1996 Dec 11
Analog electronics
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