Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS™ transistor
FEATURES
•
’Trench’
technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low thermal resistance
BSP100
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 30 V
I
D
= 6 A
g
R
DS(ON)
≤
100 mΩ (V
GS
= 10 V)
R
DS(ON)
≤
200 mΩ (V
GS
= 4.5 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect transistor in a plastic
envelope
using
’trench’
technology.
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
The BSP100 is supplied in the
SOT223
surface
mounting
package.
PINNING
PIN
1
2
3
4
gate
drain
source
drain (tab)
DESCRIPTION
SOT223
4
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 150˚C
T
j
= 25 ˚C to 150˚C; R
GS
= 20 kΩ
T
sp
= 25 ˚C
T
sp
= 100 ˚C
T
amb
= 25 ˚C
T
sp
= 25 ˚C
T
sp
= 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 65
MAX.
30
30
±
20
6
1
4.4
3.2
24
8.3
150
UNIT
V
V
V
A
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-sp
R
th j-amb
PARAMETER
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
CONDITIONS
surface mounted, FR4
board
surface mounted, FR4
board
TYP.
12
70
MAX.
15
-
UNIT
K/W
K/W
1
Continuous current rating limited by package
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS™ transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
I
AS
Non-repetitive avalanche
energy
Non-repetitive avalanche
current
CONDITIONS
Unclamped inductive load, I
AS
= 6 A;
t
p
= 0.2 ms; T
j
prior to avalanche = 25˚C;
V
DD
≤
15 V; R
GS
= 50
Ω;
V
GS
= 10 V
MIN.
-
-
BSP100
MAX.
23
6
UNIT
mJ
A
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
D(ON)
I
DSS
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 10
µA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 150˚C
T
j
= -55˚C
V
GS
= 10 V; I
D
= 2.2 A
V
GS
= 4.5 V; I
D
= 1 A
V
GS
= 10 V; I
D
= 2.2 A; T
j
= 150˚C
Forward transconductance
V
DS
= 20 V; I
D
= 2.2 A
On-state drain current
V
GS
= 10 V; V
DS
= 1 V;
V
GS
= 4.5 V; V
DS
= 5 V
Zero gate voltage drain
V
DS
= 24 V; V
GS
= 0 V;
current
V
DS
= 24 V; V
GS
= 0 V; T
j
= 150˚C
Gate source leakage current V
GS
=
±20
V; V
DS
= 0 V
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 2.3 A; V
DD
= 15 V; V
GS
= 10 V
MIN.
30
27
1
0.4
-
-
-
-
2
3.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
2
-
80
120
-
4.5
-
-
10
0.6
10
6
0.7
0.7
6
8
21
15
2.5
5
250
88
54
-
-
2.8
-
3.2
100
200
170
-
-
-
100
10
100
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
mΩ
mΩ
mΩ
S
A
A
nA
µA
nA
nC
nC
nC
ns
ns
ns
ns
nH
nH
pF
pF
pF
V
DD
= 20 V; R
D
= 18
Ω;
V
GS
= 10 V; R
G
= 6
Ω
Resistive load
Measured tab to centre of die
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS™ transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
T
sp
= 25 ˚C
MIN.
-
-
I
F
= 1.25 A; V
GS
= 0 V
I
F
= 1.25 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 25 V
-
-
-
BSP100
TYP. MAX. UNIT
-
-
0.82
69
55
6
24
1.2
-
-
A
A
V
ns
nC
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
100
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
tp = 10 us
10
100 us
d.c.
1 ms
10 ms
100 ms
BSP100
1
0.1
0
20
40
60
80
Tsp / C
100
120
140
1
10
Drain-Source Voltage, VDS (V)
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
sp
)
Fig.3. Safe operating area. T
sp
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
100
Peak Pulsed Drain Current, IDM (A)
BSP100
10
D = 0.5
0.2
1
0.1
0.05
P
D
tp
D = tp/T
0.1
0.02
single pulse
T
1E-03
1E-02
1E-01
1E+00
1E+01
0.01
1E-06
1E-05
1E-04
0
20
40
60
80
100
Tsp / C
120
140
Pulse width, tp (s)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
sp
); conditions: V
GS
≥
10 V
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
February 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS™ transistor
BSP100
6
Drain Current, ID (A)
10
9
8
7
6
5
4
3
2
1
0
0
0.2
0.4 0.6 0.8
1
1.2 1.4 1.6
Drain-Source Voltage, VDS (V)
1.8
2
VGS = 20 V
Tj = 25 C
4.2 V
4V
3.8 V
3.6 V
3.4 V
3.2 V
2
1
0
10 V
5V
5
Transconductance, gfs (S)
Tj = 25 C
4
150 C
3
0
1
2
3
4
5
6
7
Drain current, ID (A)
8
9
10
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
) ; parameter T
j
a
0.5
Drain-Source On Resistance, RDS(on) (Ohms)
3.2 V
3.4 V
3.6 V 3.8V
4V
4.2 V
Tj = 25 C
2
SOT223 30V Trench
Normalised RDS(ON) = f(Tj)
0.4
1.5
0.3
1
0.2
VGS =5 V
10V
20V
0
0
1
2
3
4
5
6
Drain Current, ID (A)
7
8
9
10
0.1
0.5
0
-50
0
50
Tj / C
100
150
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
VGS(TO) / V
4
Drain current, ID (A)
10
9
8
7
6
5
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Tj = 25 C
150 C
VDS > ID X RDS(ON)
3
max.
typ.
2
1
min.
0
-60 -40 -20
0
20
40 60
Tj / C
80 100 120 140
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
February 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS™ transistor
BSP100
1E-01
Sub-Threshold Conduction
10
9
Source-Drain Diode Current, IF (A)
VGS = 0 V
1E-02
min
typ
max
8
7
6
5
4
Tj = 25 C
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
1E-03
150 C
1E-04
1E-05
1E-06
0
1
2
3
4
5
Drain-Source Voltage, VSDS (V)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Non-repetitive Avalanche current, IAS (A)
10
BSP100
25 C
Capacitances, Ciss, Coss, Crss (pF)
1000
Ciss
1
100
Coss
Crss
VDS
Tj prior to avalanche =125 C
tp
ID
10
0.1
1
10
Drain-Source Voltage, VDS (V)
100
0.1
1E-06
1E-05
1E-04
Avalanche time, tp (s)
1E-03
1E-02
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
p
);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ID = 2.3A
Tj = 25 C
VDD = 15 V
1
2
3
4
5
6
7
Gate charge, QG (nC)
8
9
10
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
February 1999
5
Rev 1.000
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