The HMXCMP01 is fabricated on a radiation hardened SOI-IV Silicon-On-Insulator (SOI)
CMOS process with very low power consumption operating on a single supply. It is
designed for low input current, low offset voltage and fast response time while
operating over the full military temperature range.
Honeywell’s SOI-IV technology is radiation hardened through the use of advanced
and proprietary design, layout and process hardening techniques.
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Functional
Diagram
Signal Definitions
Top View
VDDD
VOUT
NC
VIN+
1
2
3
4
+
–
Pin
8
7
6
5
VSS
VDD
NC
VIN–
1
2
3
4
5
6
7
8
Signal
VOUT
VDDD
N/C
VIN+
VIN-
N/C
VDD
VSS
Description
Output
Digital Power Supply 3.3V or 5V
No Connection
+ Input
- Input
No Connection
Analog Power Supply.
Ground
Block Diagram
VDD
VIN+
VIN–
VDDD
+
–
VOUT
The comparator has a low power two-
stage architecture. The first stage is a
differential amplifier with NMOS and
PMOS input differential pairs with
constant gm (transconductance).
This provides input rail-to-rail operation.
The second stage is made up of two
inverters that provide logic output at 3.3V
or 5V (depending on the value of VDDD).
Note that to avoid crow bar currents at
Logic high outputs, VDDD must be lower
or equal to VDD.
Radiation Characteristics
Total Ionizing Radiation Dose
The device will meet all stated functional and electrical
specifications after the specified total ionizing radiation dose.
All electrical and timing performance parameters will remain
within specifications, post rebound (based on extrapolation),
after an operational period of 15 years. Total dose hardness is
assured by wafer level testing of process monitor transistors using
10 KeV X-ray. Parameter correlations have been made between
10 KeV X-rays applied at a dose rate of 5x10
5
rad(SiO
2
)/min at
T= 25°C and gamma rays (Cobalt 60 source) to ensure that
wafer level X-ray testing is consistent with standard military
radiation test environments.
Transient Pulse Ionizing Radiation
The Comparator is capable of functioning during and after exposure
to a transient ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under recommended
operating conditions. It is recommended to provide external power
supply decoupling capacitors to maintain VDD and VDDD voltage
levels during transient events. The Comparator will meet any functional
or electrical specification after exposure to a radiation pulse up to the
transient dose rate survivability specification, when applied under
recommended operating conditions. Note that the current conducted
during the pulse by the Comparator inputs, outputs, and power supply
may significantly exceed the normal operating levels. The application
design must accommodate these effects.
Neutron Radiation
The Comparator will meet any functional or timing specification after
exposure to the specified neutron fluence under recommended
operating or storage conditions.
Latchup
The Comparator will not latch up due to any of the above radiation
exposure conditions when applied under recommended operating
conditions. Fabrication with the SOI substrate material provides
oxide isolation between adjacent PMOS and NMOS transistors
and eliminates any potential SCR latchup structures. Sufficient
transistor body tie connections to the p- and n-channel substrates
are made to ensure no source/drain snapback occurs.
Radiation-Hardness Ratings (1)
Parameter
Total Dose (2)
Transient Dose Rate Upset
Transient Dose Rate Survivability
Neutron Fluence
Limits
≥3x10
5
≥2x10
10
≥2x10
9
≥1x10
12
≥1x10
14
Units
rad(Si)
rad(Si)/s
rad(Si)/s
N/cm
2
Test Conditions
VDD = 5V, VDDD = 3.3V
Pulse width=20ns, VDD=5V, VDDD=3.3V
Pulse width=3µs, VDD=5V, VDDD=5V
Pulse width=20ns and 3µs,
VDD=5V, VDDD=3.3V and 5V
1MeV equivalent energy, Unbiased, T
A
=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Parts tested to 300K rad without accelerated annealing.
Absolute Maximum Ratings (1)(2)
Parameter
Analog Supply Voltage
Digital Supply Voltage
Input Voltage
Input Current
Output Voltage
(3)
(3)
(3)
Symbol
VDD
VDDD
VIN+, VIN-
IVIN+, IVIN-
VOUT
P
D
T
STG
(4)
-
0
JC
T
J
T
LMAX
Min
-0.5
-0.5
-0.5
-50
-0.5
Limits
Max
6.5
6.5
VDD+0.5
50
Units
V
V
V
mA
V
Seconds
mW
°C
°C/W
°C
°C
V
VDDD+0.5
1
200
Output Short-Circuit Duration
Power Dissipation
Storage Temperature Range
Thermal Resistance, Junction to Case
Junction Temperature
Lead Temperature (Soldering, 10 seconds)
ESD HBM 1.5K ohms, 100pF
-65
150
22.3
175
300
500
(1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
(2) VSS = 0 volts.
(3) Input and Output terminals are diode-clamped to the power supply rail and ground. Input and Output signals that can swing more than 0.5 volts beyond the power supply rails should be
current limited to 50 mA or less.
(4) By analysis.
Absolute Maximum Ratings (1)(2)
Parameter
Analog Power Supply
Digital Power Supply
Operating Temperature Steady State
Input Slew Rate (2)
(1) All voltages are with respect to VSS =0.0V.
(2) For inputs steps > 0.7 volts.
Symbol
VDD
VDDD
T
C
Min
4.75
3.135
-55
Limits
Max
5.25
5.25
125
12
Units
V
V
°C
V/µS
Electrical Characteristics
VDD = 5.0 V ± 5%, VDDD = 3.3 ± 5%, VSS = 0.0 V, TC = -55 °C to 125 °C (unless otherwise specified)
Parameter
Analog Supply Current
Digital Supply Current
Power-Supply Rejection Ratio
Common-Mode Voltage Range (1)
Input Offset Voltage
Input Bias Current
Input Offset Current
Input Capacitance (1)
Common-Mode Rejection Ratio
Output Rise Time (1)
Output Fall Time (1)
Propagation Delay (1)
Output Short-Circuit Current (1)
High Level Output Voltage (minimum)
Symbol
I
DD
I
DDD
PSRR
V
CMR
V
OS
I
B
I
OS
C
IN
CMRR
t
RISE
t
FALL
t
PD
I
SC
V
OH
Min
—
—
60
0
-24
-1.0
-2.0
—
48
—
—
—
5
5
VDDD-0.5
VDDD-0.5
Max
900
1
—
5
24
1.0
2.0
10
—
30
30
125
50
85
—
Unit
µA
mA
dB
V
mV
nA
nA
pF
dB
ns
ns
ns
mA
V
Conditions
VIN+ = 0.5 V, VIN- = 0.0V
VIN+ = 0.5 V, VIN- = 0.0V
VDD = 4.75V and 5.25V, VDDD=3.3V, V
CM
= 2.5V
V
DD
= 5V
V
CM
= VDD/2
VIN+ = 2.5 V, VIN- = 2.0V
VIN+ = 2.5 V, VIN- = 2.0V
Common Mode=0V and 5V
C
L
= 15pF, 100mV overdrive
C
L
= 15pF, 100mV overdrive
C
L
= 15pF, 100mV overdrive
VDDD = 3.3V ± 5% (2)
VDDD = 5.0V ± 5% (2)
VDDD = 3.3V ± 5%, I
OH
= -5ma
VIN+ = 2.5 V, VIN- = 2.0 V
VDDD = 5V ± 5%, I
OH
= -5ma
VIN+ = 2.5 V, VIN- = 2.0 V
Low Level Output Voltage (maximum)
V
OL
—
0.5
V
VDDD=3.3V,
I
OL
= 5mA
VIN+ = 2.0 V, VIN- = 2.5 V
(1) This parameter is guaranteed by design.
(2) VOUT = VDDD or VSS, 1 second maximum.
Package Outline Dimensions
Dimensions in inches.
½½½½
½½½½
½½½½½½½½½½½
½½½½
½½½½
½½½½
½½½½
½½½½
½½½½½½½½
½½½½½½
½½½½
½½½½½½½½½½½½½½
½½½½½½½½½½½
½½½½
½½½½½½½½½½½
½½½½½½½½
½½½½
Reliability
For many years Honeywell has been producing integrated circuits
that meet the stringent reliability requirements of space and
defense systems. Honeywell has delivered hundreds of thousands
of QML parts since first becoming QML qualified in 1990. Using
this proven approach Honeywell will assure the reliability of the
products manufactured with the SOI CMOS process technology.
This approach includes adhering to Honeywell’s General
Manufacturing Standards for:
• Designing in reliability by establishing electrical rules based on
wear out mechanism characterization performed on specially
designed test structures (electromigration, TDDB, hot carriers,
negative bias temperature instability, radiation)
• Utilizing a structured and controlled design process
• A statistically controlled wafer fabrication process with a
continuous defect reduction process
• Individual wafer lot acceptance through process monitor testing
(includes radiation testing)
• The use of characterized and qualified packages
• A thorough product testing program based on MIL-PRF-38535
and MIL-STD 883.
Qualification and Screening
The SOI CMOS technology is qualified by Honeywell after meeting
the criteria of the General Manufacturing Standards and is also
QML Qualified. This qualification is the culmination of years of
development, testing, documentation, and on-going process control.
The test flow includes screening units with the defined flow
(Class V and Q+ equivalent) and the appropriate periodic or lot
conformance testing (Groups B, C, D, and E). Both the process
and the products are subject to period or lot based Technology
Conformance Inspection (TCI) and Quality Conformance
Inspection (QCI) tests, respectively, as defined by Honeywell’s
Quality Management Plan.
Honeywell delivers products that are screened to two levels
including Engineering Models and Flight Units. EMs are
available with limited screening for prototype development
and evaluation testing.
Group A
Group B
Group C
Group D
Final Lot Acceptance Electrical Tests
Mechanical – Dimensions (1), Bond Strength, Solvents, Die Shear,
Solderability, Lead Integrity, Seal, Acceleration
Life Tests – 1000 hours at 125°C or equivalent
Package related mechanical tests – Shock, Vibration, Accel, Salt (1),
Seal, Lead Finish Adhesion, Lid Torque, Thermal Shock, Temp Cycle,
Moisture Resistance
Group E
Radiation Tests
(1) Testing performed by package supplier.
Ordering Information (1)
H
Source
H = Honeywell
MX
Process
MX = Mixed Signal SOI
CMP01
Part Number
D
Package Designation
D = 40 Lead Flatpack
- = Bare Die (3)
Z
F
Total Dose Hardness
F = 3x10
5
rad (Si)
N = No Level Guaranteed (2)
Screen Level
Z = Class S \QML V Equivalent (3)
Y = Class B \QML Q + Equivalent (3)
E = Eng. Model (2)
(1)
(2)
(3)
(4)
Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-763-954-2474 for further information.
Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, no radiation guaranteed.
Bare die do not receive any reliability screening.
This is an equivalent screening flow but this device is not QML qualified.
QCI Testing (1)
Classification
QML Q+ Equivalent
QML V Equivalent
QCI Testing
No lot specific testing performed. (2)
Lot specific testing required in accordance with MIL-PRF-38535 Appendix B.
(1) QCI groups, subgroups and sample sizes are defined in MIL-PRF38535 and the Honeywell Quality Management Plan. Quarterly testing is done in accordance with the Honeywell QM Plan.
(2) If customer requires lot specific testing, the purchase order must indicate specific tests and sample sizes.
This product and related technical data is subject to the U.S. Department of State International Traffic in Arms Regulations (ITAR) 22 CFR 120-130 and may not be exported, as defined by the
ITAR, without the appropriate prior authorization from the Directorate of Defense Trade Controls, United States Department of State. Diversion contrary to U.S. export laws and regulations is
prohibited. This datasheet includes only basic marketing information on the function of the product and therefore is not considered technical data as defined in 22CFR 120.10.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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