ispLSI
®
3256E Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispLSI 3256E
Ordering Part Number
ispLSI 3256E-70LB320
ispLSI 3256E-100LB320
ispLSI 3256E-70LQA
ispLSI 3256E-100LQA
Product Status
Discontinued
Reference PCN
PCN#09-10
PCN#12-09
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
ispLSI 3256E
®
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 256 I/O Pins
— 12000 PLD Gates
— 512 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
2
®
Functional Block Diagram
ORP
H3
H2
ORP
ORP
G3
D Q
ORP
H1
H0
G2
G1
G0
Boundary
Scan
ORP
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
ORP
A2
Array
D Q
A1
OR
D Q
F2
F1
ORP
• HIGH PERFORMANCE E CMOS TECHNOLOGY
—
f
max
= 100 MHz Maximum Operating Frequency
—
t
pd
= 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
AND Array
D Q
A3
D Q
Twin
GLB
F0
OR
D Q
ORP
D Q
B1
B2
D Q
E2
E1
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
Global Routing Pool
B3
E0
C0
C1
C2
C3
D0
D1
D2
D3
ORP
ORP
ORP
ORP
0139A/3256E
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Description
The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connectivity between all of these ele-
ments. The ispLSI 3256E features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256E offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3256E device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256E
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays and eight
outputs which can be configured to be either combinato-
rial or registered. All Twin GLB inputs come from the
GRP.
Copyright © 2010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
March 2010
3256e_10
1
ORP
ORP
B0
Array
E3
ORP
ORP
A0
F3
Specifications
ispLSI 3256E
Functional Block Diagram
Figure 1. ispLSI 3256E Functional Block Diagram
I/O 255
I/O 253
I/O 251
I/O 249
I/O 247
I/O 245
I/O 243
I/O 241
I/O 239
I/O 237
I/O 235
I/O 233
I/O 231
I/O 229
I/O 227
I/O 225
I/O 223
I/O 221
I/O 219
I/O 217
I/O 215
I/O 213
I/O 211
I/O 209
I/O 207
I/O 205
I/O 203
I/O 201
I/O 199
I/O 197
I/O 195
I/O 193
BSCAN/ispEN
TCLK/SCLK
I/O 254
I/O 252
I/O 250
I/O 248
I/O 246
I/O 244
I/O 242
I/O 240
I/O 238
I/O 236
I/O 234
I/O 232
I/O 230
I/O 228
I/O 226
I/O 224
I/O 222
I/O 220
I/O 218
I/O 216
I/O 214
I/O 212
I/O 210
I/O 208
I/O 206
I/O 204
I/O 202
I/O 200
GOE0
GOE1
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
TOE
Generic
Logic
Blocks
Input Bus
ORP
ORP
Input Bus
ORP
ORP
ISP and
Boundary
Scan TAP
I/O 198
I/O 196
I/O 194
I/O 192
TMS/MODE
TDI/SDI
TRST
H3
H2
H1
H0
G3
G2
G1
G0
TDO/SDO
I/O 190
I/O 188
I/O 186
I/O 184
I/O 182
I/O 180
I/O 178
I/O 176
I/O 174
I/O 172
I/O 170
I/O 168
I/O 166
I/O 164
I/O 162
I/O 160
I/O 191
I/O 189
I/O 187
I/O 185
I/O 183
I/O 181
I/O 179
I/O 177
I/O 175
I/O 173
I/O 171
I/O 169
I/O 167
I/O 165
I/O 163
I/O 161
Input Bus
A1
F2
I/O 25
I/O 27
I/O 29
I/O 31
I/O 24
I/O 26
I/O 28
I/O 30
ORP
A3
F0
Input Bus
B1
E2
I/O 57
I/O 59
I/O 61
I/O 63
I/O 56
I/O 58
I/O 60
I/O 62
ORP
ORP
I/O 49
I/O 51
I/O 53
I/O 55
I/O 48
I/O 50
I/O 52
I/O 54
Input Bus
I/O 41
I/O 43
I/O 45
I/O 47
I/O 40
I/O 42
I/O 44
I/O 46
ORP
ORP
I/O 33
I/O 35
I/O 37
I/O 39
I/O 32
I/O 34
I/O 36
I/O 38
Global Routing Pool
(GRP)
ORP
I/O 17
I/O 19
I/O 21
I/O 23
I/O 16
I/O 18
I/O 20
I/O 22
A2
F1
Input Bus
I/O 9
I/O 11
I/O 13
I/O 15
I/O 8
I/O 10
I/O 12
I/O 14
ORP
ORP
I/O 1
I/O 3
I/O 5
I/O 7
I/O 0
I/O 2
I/O 4
I/O 6
A0
F3
B0
E3
I/O 158
I/O 156
I/O 154
I/O 152
I/O 150
I/O 148
I/O 146
I/O 144
I/O 142
I/O 140
I/O 138
I/O 136
I/O 134
I/O 132
I/O 130
I/O 128
I/O 159
I/O 157
I/O 155
I/O 153
I/O 151
I/O 149
I/O 147
I/O 145
I/O 143
I/O 141
I/O 139
I/O 137
I/O 135
I/O 133
I/O 131
I/O 129
B2
E1
B3
E0
C0
C1
C2
C3
D0
D1
D2
D3
Megablock
ORP
ORP
ORP
ORP
Input Bus
Input Bus
RESET
I/O 97 I/O 96
I/O 99 I/O 98
I/O 101 I/O 100
I/O 103 I/O 102
I/O 104
I/O 106
I/O 108
I/O 110
I/O 112
I/O 114
I/O 116
I/O 118
I/O 120
I/O 122
I/O 124
I/O 126
I/O 64
I/O 66
I/O 68
I/O 70
I/O 72
I/O 74
I/O 76
I/O 78
I/O 80
I/O 82
I/O 84
I/O 86
I/O 88
I/O 90
I/O 92
I/O 94
Y0
Y1
Y2
Y3
Y4
CLK 0
CLK 1
CLK 2
IOCLK 1
IOCLK 0
0139isp/3256E
I/O 65
I/O 67
I/O 69
I/O 71
I/O 73
I/O 75
I/O 77
I/O 79
I/O 81
I/O 83
I/O 85
I/O 87
I/O 89
I/O 91
I/O 93
I/O 95
I/O 105
I/O 107
I/O 109
I/O 111
I/O 113
I/O 115
I/O 117
I/O 119
2
I/O 121
I/O 123
I/O 125
I/O 127
Specifications
ispLSI 3256E
Description (continued)
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 256 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
The 256 I/O Cells are grouped into 16 sets of 16 bits.
Pairs of these I/O groups are associated with a logic
Megablock through the use of the ORP. Each Megablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
That PTOE signal can be generated within any GLB in the
Megablock. Each I/O cell can select either a Global OE
or a PTOE.
Four Twin GLBs, 32 I/O Cells and two ORPs are con-
nected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
32 I/O cells by the ORP. The ispLSI 3256E device
contains eight of these Megablocks.
Clocks in the ispLSI 3256E device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
The table below lists key attributes of the device along
with the number of resources available.
An additional feature of the ispLSI 3256E is its Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
The ispLSI 3256E supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Key Attributes of the ispLSI 3256E
Attribute
Quantity
32
Twin GLBs
Registers
I/O Pins
512
256
5
2
1
Global Clocks
Global OE
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.
Test OE
Table - 003/3256E
3
Specifications
ispLSI 3256E
Absolute Maximum Ratings
1
Supply Voltage V
cc
........................................................................... -0.5 to +7.0V
Input Voltage Applied ........................................................................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..................................................... -2.5 to V
CC
+1.0V
Storage Temperature ........................................................................ -65 to 150°C
Case Temp. with Power Applied ...................................................... -55 to 125°C
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Max. Junction Temp. (T
J
) with Power Applied (304-Pin PQFP) ...... 150°C
Max. Junction Temp. (T
J
) with Power Applied (320-Ball BGA) ........ 140°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
MIN.
0
0
4.75
2.0
MAX.
70
5.25
0.8
UNITS
°C
V
V
V
T
A
V
CC
V
IL
V
IH
Ambient Temperature
Supply Voltage
Input Low Voltage
Input High Voltage
V
CC
+1
Table 2-0005/3256E
Capacitance (T
A
=25°C,f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
10
15
UNITS
pf
pf
TEST CONDITIONS
C
1
C
2
I/O Capacitance
V
CC
= 5.0V, V
I/O
= 2.0V
V
CC
= 5.0V, V
Y
= 2.0V
Table 2-0006/3256E
Clock Capacitance
Data Retention Specifications
PARAMETER
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Data Retention
ispLSI Erase/Reprogram Cycles
Cycles
Table 2-0008/3256E
4
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