2. GENERAL DESCRIPTION ........................................................................................................................................... 4
3. ORDERING INFORMATION ........................................................................................................................................ 4
11. DC CHARACTERISTICS (x4/x8) ................................................................................................................................ 9
12. DC CHARACTERISTICS (x16)................................................................................................................................... 10
13. AC OPERATING TEST CONDITIONS ....................................................................................................................... 11
14. OPERATING AC PARAMETER ................................................................................................................................. 12
15. AC CHARACTERISTICS ............................................................................................................................................ 13
18. SIMPLIFIED TRUTH TABLE ...................................................................................................................................... 18
-3-
K4S560432N
K4S560832N
K4S561632N
datasheet
Rev. 1.0
SDRAM
1. KEY FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• Lead-Free & Halogen-Free Package
• RoHS compliant
2. GENERAL DESCRIPTION
The K4S560432N / K4S560832N / K4S561632N is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4
bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous
design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, pro-
grammable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory sys-