WT62P1
Data Sheet Rev. 1.01
GENERAL DESCRIPTION
The WT62P1 is a microcontroller for digital controlled monitor with Universal Serial Bus (USB) interface.
It contains an 8-bit CPU, 32K bytes flash memory, 512 bytes RAM, 14 PWMs, parallel I/Os, SYNC signal
2
processor, timer, DDC1/2B interface, master/slave I C interface, low speed USB device module, 6-bit
A/D converter and watch-dog timer.
FEATURES
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8-bit 6502 compatible CPU with 6MHz operating frequency
32768 bytes flash memory, 512 bytes SRAM
12MHz crystal oscillator
14 channels 8-bit PWM outputs
Sync signal processor with H+V separation, H/V frequency counter, H/V polarity detection/control and
clamp pulse output
Six free-running sync signal outputs (Horizontal frequency up to 106KHz)
Self-test pattern
DDC1/2B supported
2
Fast mode master/slave I C interface (up to 400KHz)
Embedded USB function with endpoint 0 and endpoint 1
Built-in 3.3V regulator for USB tranceiver
Watch-dog timer
Maximum 28 programmable I/O pins
One 8-bit programmable timer
6-bit A/D converter with 4 selectable inputs
One external interrupt request input
Low V
DD
reset
ORDERING INFORMATION
Package Type
42-pin PDIP
42-pin Shrink PDIP
40-pin PDIP
28-pin skinny PDIP
44-pin SOP
Part Number
WT62P1-N42
WT62P1-K42
WT62P1-N40
WT62P1-N28
WT62P1-S44
Weltrend Semiconductor, Inc.
Page 2
WT62P1
Data Sheet Rev. 1.01
PIN CONFIGURATION
42-pin PDIP
42-pin SPDIP
D+
PWM2
PWM1
PWM0
RESET/3V3
VDD
GND
OSCO
OSCI
PB5/SDA2
PB4/SCL2
PB3/PAT
PB2
PB1/HFI
PB0/HFO
IRQ
PC7/SOGIN
PC6
PC5
PC4
PC3/AD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
D-
VIN
HIN
PWM3
PD5/PWM4
PD4/PWM5
PD3/PWM6
PD2/PWM7
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12
PA5/PWM11
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1
PA0/SDA1
PC0/AD0
PC1/AD1
PC2/AD2
PWM2
PWM1
PWM0
RESET/3V3
VDD
GND
OSCO
OSCI
PB5/SDA2
PB4/SCL2
PB3/PAT
PB2
PB1/HFI
PB0/HFO
IRQ
PC7/SOGIN
PC6
PC5
PC4
PC3/AD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
VIN
HIN
PWM3
PD5/PWM4
PD4/PWM5
PD3/PWM6
PD2/PWM7
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12
PA5/PWM11
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1
PA0/SDA1
PC0/AD0
PC1/AD1
PC2/AD2
40-pin PDIP
WT62P1-N42
WT62P1-K42
33
32
31
30
29
28
27
26
25
24
23
22
WT62P1-N40
31
30
29
28
27
26
25
24
23
22
21
44-pin SOP
D+
PWM2
PWM1
PWM0
RESET/3V3
VDD
1
2
3
4
5
6
7
GND
OSCO
OSCI
PB5/SDA2
PB4/SCL2
PB3/PAT
PB2
PB1/HFI
PB0/HFO
IRQ
PC7/SOGIN
PC6
PC5
PC4
PC3/AD3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
PD3/PWM6
PD2/PWM7
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12
PA5/PWM11
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1
PA0/SDA1
PC0/AD0
PC1/AD1
PC2/AD2
D-
VIN
HIN
PWM3
PD5/PWM4
PD4/PWM5
PA5/PWM11
PA6/PWM12
PA7/PWM13/CLAMP
PD0/VOUT
PD1/HOUT
HIN
VIN
RESET/3V3
VDD
GND
OSCO
OSCI
PB5/SDA2
PB4/SCL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin Skinny PDIP
28
27
26
25
24
23
22
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1
PA0/SDA1
PC0/AD0
PC1/AD1
PC2/AD2
PC3/AD3
PC4
PC5
PC6
PC7
IRQ
WT62P1-N28
21
20
19
18
17
16
15
WT62P1-S44
33
32
31
30
29
28
27
26
25
24
23
Weltrend Semiconductor, Inc.
Page 3
WT62P1
Data Sheet Rev. 1.01
PIN DESCRIPTION
Pin No.
44 42 40 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
-
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
-
37
38
39
40
41
42
-
1
2
3
4
5
-
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
-
36
37
38
39
40
-
-
-
-
-
8
9
-
10
11
12
13
14
-
-
-
-
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
-
-
-
-
-
-
6
7
-
Pin Name
D+
PWM2
PWM1
PWM0
/RESET/3V3
VDD
NC
GND
OSCO
OSCI
PB5/ SDA2
PB4/ SCL2
PB3/PAT
PB2
PB1/HFI
PB0/HFO
/IRQ
PC7/SOGIN
PC6
PC5
PC4
PC3/AD3
PC2/AD2
PC1/AD1
PC0/AD0
PA0/SDA1
PA1/SCL1
PA2/PWM8
PA3/PWM9
PA4/PWM10
PA5/PWM11
PA6/PWM12
PA7/PWM13/
CLAMP
PD0/VOUT
PD1/HOUT
PD2/PWM7
PD3/PWM6
NC
PD4/PWM5
PD5/PWM4
PWM3
HIN
VIN
D-
I/O
I/O
O
O
O
I
Description
USB D+ signal.
PWM2 output (10V open-drain).
PWM1 output (5V open-drain).
PWM0 output (5V open-drain).
Reset input and +3.3V regulator output for USB tranceiver power
supply.
+5V power supply.
No Connection.
Ground.
12MHz oscillator output.
12MHz oscillator input.
2
Port B5 or I C interface data line.
2
Port B4 or I C interface clock line.
Port B3 or test pattern output
Port B2.
Port B1 or half frequency divider input.
Port B0 or half frequency divider output.
Interrupt request input, A low level on this can generate interrupt.
Port C7 or Sync on Green input.
Port C6.
Port C5.
Port C4.
Port C3 or ADC input 3.
Port C2 or ADC input 2.
Port C1 or ADC input 1.
Port C0 or ADC input 0.
Port A0 or DDC interface SDA pin.
Port A1 or DDC interface SCL pin.
Port A2 or PWM8 output.
Port A3 or PWM9 output.
Port A4 or PWM10 output.
Port A5 or PWM11 output.
Port A6 or PWM12 output.
Port A7 or PWM13 output or clamp pulse output.
Port D0 or Vsync output.
Port D1 or Hsync output.
Port D2 or PWM7 output.
Port D3 or PWM6 output.
No Connection.
Port D4 or PWM5 output.
Port D5 or PWM4 output.
PWM3 output (10V open-drain).
Hsync Input.
Vsync input.
USB D- signal.
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
Weltrend Semiconductor, Inc.
Page 4
WT62P1
Data Sheet Rev. 1.01
FUNCTIONAL DESCRIPTION
CPU
8-bit 6502 compatible CPU operates at 6MHz. Address bus is 16-bit and data bus is 8-bit.
The non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher
priority. The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority.
Please refer the 6502 reference menu for more detail.
RAM
512 bytes RAM. Address is located from $0080h to $00FFh and $0180h to $02FFh.
RAM from $0200h to $027Fh and $0280h to $02FFh can be disabled individually to emulate different
RAM size IC. (see Register $0FFFh)
ROM
32768 bytes flash memory for program. Address is located from $8000h to $FFFFh.
The following addresses are reserved for special purpose :
$FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector.
$FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector.
$FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector.
$0000h
:
Registers
$003Fh
$0040h
Reserved
:
$007Fh
$0080h
:
128 bytes RAM
$00FFh
$0100h
Reserved
:
$017Fh
$0180h
:
384 bytes RAM
$02FFh
$0300h
Reserved
:
$0FFEh
$0FFFh Configuration Register
$1000h
Reserved
:
$7FFFh
$8000h
:
:
Flash ROM
:
$FFFFh
System Reset
There are four reset sources of this controller. Fig.1 shows the block diagram of reset logic.
Weltrend Semiconductor, Inc.
Page 5
WT62P1
Data Sheet Rev. 1.01
%&'
&
(
% )
Fig. 1 Reset Signals
External Reset
A low level on the RESET/3.3V pin will generate reset.
Illegal address Reset
When the address bus of CPU goes to illegal address, a reset pulse will be generated.
The illegal address is defined as $0040h~$007Fh, $0300h~$0FFEh and $1000h~$7FFFh.
Low VDD Voltage Reset
When VDD is below 3.9V, an internal reset signal is generated. The reset signal will last 2.048 ms after
the voltage is higher than 3.9V.
Watchdog Timer Reset
If a time-out happens when watchdog timer is enabled, a reset pulse is generated. Please refer
watchdog timer section for more information.
Weltrend Semiconductor, Inc.
Page 6
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