datasheet
EEWORLDEEWORLDEEWORLD
Datasheet
Part Number

Keyword

Search
Keyword

Part Number

Search
Datasheet> All Categories > logic> logic> 8530DY-01LF
PDF
Preview

8530DY-01LF

Description
Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48
Categorylogic    logic   
File Size170KB，15 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric Compare View All

8530DY-01LF Overview

Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48

8530DY-01LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLFQFP, QFP48,.35SQ,20
Contacts48
Reach Compliance Codecompliant
ECCN codeEAR99
series8530
Input adjustmentDIFFERENTIAL
JESD-30 codeS-PQFP-G48
JESD-609 codee3
length7 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals48
Actual output times16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP48,.35SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup2 ns
propagation delay (tpd)2 ns
Certification statusNot Qualified
Same Edge Skew-Max（tskwd）0.075 ns
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width7 mm

8530DY-01LF Preview

Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
Sixteen differential 3.3V LVPECL outputs
•
CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 500MHz
•
Translates any single-ended input signal to
3.3V LVPECL levels with a resistor bias on nCLK input
•
Output skew: 75ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Additive phase jitter, RMS: 0.03ps (typical)
•
3.3V output operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS8530-01 is a low skew, 1-to-16 Differen-
tial-to-3.3V LVPECL Fanout Buffer and a mem-
HiPerClockS™
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input
levels. The high gain differential amplifier accepts peak-to-
peak input voltages as small as 150mV as long as the com-
mon mode voltage is within the specified minimum and maxi-
mum range.
IC
S
Guaranteed output and part-to-part skew characteristics make
the ICS8530-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK
nCLK
P
IN
A
SSIGNMENT
nCLK
V
CCO
Q15
nQ15
Q14
nQ14
V
EE
Q13
nQ13
Q12
nQ12
V
CCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
V
CCO
Q11
nQ11
Q10
nQ10
V
EE
Q9
nQ9
Q8
nQ8
V
CCO
V
CC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8530-01
CLK
V
CCO
nQ0
Q0
nQ1
Q1
V
EE
nQ2
Q2
nQ3
Q3
Vcco
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8530DY-01
www.icst.com/products/hiperclocks.html
1
V
CCO
nQ4
Q4
nQ5
Q5
V
EE
nQ6
Q6
nQ7
Q7
V
CCO
V
CC
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Type
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Core supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels..
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 11, 14, 24,
25, 35, 38, 48
2, 3
4, 5
6, 19, 30, 43
7, 8
9, 10
12, 13
15, 16
17, 18
20, 21
22, 23
26, 27
28, 29
36
37
39, 40
41, 42
44, 45
46, 47
NOTE:
Pullup
and
Name
V
CCO
Q11, nQ11
Q10, nQ10
V
EE
Q9, nQ9
Q8, nQ8
V
CC
Q7, nQ7
Q6, nQ6
Q5, nQ5
Q4, nQ4
Q3, nQ3
Q2, nQ2
CL K
Input
Pulldown Non-inver ting differential clock input.
nCLK
Input
Pullup
Inver ting differential clock input.
Differential output pair. LVPECL interface levels.
Q15, nQ15
Output
Q14, nQ14
Output
Differential output pair. LVPECL interface levels.
Output
Differential output pair. LVPECL interface levels.
Q13, nQ13
Differential output pair. LVPECL interface levels.
Q12, nQ12
Output
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q15
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ15
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8530DY-01
www.icst.com/products/hiperclocks.html
2
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Input/core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
140
Units
V
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
-2V.
8530DY-01
www.icst.com/products/hiperclocks.html
3
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Test Conditions
IJ 500MHz
Minimum
1
88
106.25MHz, Integration
Range: 12KHz to 20MHz
20% to 80% @ 50MHz
20% to 80% @ 50MHz
0.03
300
300
700
700
53
Typical
Maximum
500
2
75
250
Units
MHz
ns
ps
ps
ps
ps
ps
%
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise Time
Output Fall Time
odc
Output Duty Cycle
47
50
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8530DY-01
www.icst.com/products/hiperclocks.html
4
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
-60
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 106.25MHz (12KHz to 20MHz)
= 0.03ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
8530DY-01
www.icst.com/products/hiperclocks.html
5
REV. E MAY 19, 2006
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

8530DY-01LF Related Products

8530DY-01LF 8530DY-01LFT
Description Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48 Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code QFP QFP
package instruction LFQFP, QFP48,.35SQ,20 LFQFP, QFP48,.35SQ,20
Contacts 48 48
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
series 8530 8530
Input adjustment DIFFERENTIAL DIFFERENTIAL
JESD-30 code S-PQFP-G48 S-PQFP-G48
JESD-609 code e3 e3
length 7 mm 7 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Number of functions 1 1
Number of terminals 48 48
Actual output times 16 16
Maximum operating temperature 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LFQFP LFQFP
Encapsulate equivalent code QFP48,.35SQ,20 QFP48,.35SQ,20
Package shape SQUARE SQUARE
Package form FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 2 ns 2 ns
propagation delay (tpd) 2 ns 2 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.075 ns 0.075 ns
Maximum seat height 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) MATTE TIN
Terminal form GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 7 mm 7 mm

Recommended Resources

Possible causes of unexplained device failure

JZLF-31F thyristor automatic excitation device circuit

Current measurement circuit with a range of 100mA to 1mA

Nickel Cadmium Battery Charger

PI regulator circuit

Stabilized power supply detection circuit

MSP430 microcontroller framework program
[i=s] This post was last edited by Jacktang on 2017-4-24 14:31 [/i] [b]/*********************************************************************************\[/b] [b]File name: main.c[/b] [b]Description: ...
Jacktang Microcontroller MCU
Ask for past exam questions
Hello masters, this is my first time participating in the TI Cup. I wonder if anyone has the real questions from the second stage of the 2010 TI Cup, which is the national competition, or the predicte...
foreverontheroa TI Technology Forum
Chapter 3 File I/O
3.1 Introduction 35 3.2 File Descriptors 35 3.3 open Function 35 3.4 creat Function 37 3.5 close Function 37 3.6 lseek Function 38 3.7 read Function 40 3.8 write Function 41 3.9 I/O Efficiency 41 3.10...
謃塰 Linux and Android
N reasons not to use PIC vs. N reasons to use PIC
In fact, many colleagues have already stated several reasons for not using PIC (i.e., PIC is inferior to other types of microcontrollers in some important indicators), so I will not repeat them. -A fe...
tiankai001 Microchip MCU
Circuit system design and production process and some issues that need attention
[size=4]Electronic circuit design involves a lot of things. First of all, you need to design the circuit diagram according to specific needs and applications. This is the most important part of the en...
Jacktang Analogue and Mixed Signal
AVR
BBBBBBBBBBBBBBBBBBBBBBBBBB...
weiren Microchip MCU
Shortcut:   00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components

  1. BUX32B
  2. T551B107M025AH4251
  3. CDRH7D16NP-6R8PB
  4. NGCN/1HP1F3AX
  5. 93932-864
  6. CRCW06038662F100RT1-E3
  7. 0603A560JAXVMLS
  8. PHJ-6P2C-12-RY-2
  9. AME8834AEIV250L
  10. SMAJ45A
  11. A2005WR-N1-2x2P
  12. C2521HFB-5P-RD

Popular Articles

  1. Real-time clock demonstration: millisecond timing output; serial port output; use of interrupts
  2. 51 MCU-Serial Communication Introduction
  3. Nayuki Tea’s affiliated companies have added “integrated circuit design” to their business scope
  4. Renesas Electronics Accelerates Deep Learning Development for ADAS and Autonomous Driving Applications
  5. How to Bridge a Class D Amplifier
  6. Supporting "China Chip", Jihu GitLab helps AI chip companies build DevOps systems
  7. Xiaomi smart camera obtains BSI IoT security Kitemark certification
  8. Keysight Technologies Launches Radar Scenario Simulator Solution
  9. ATmega168 External RC Oscillator
  10. With a total investment of 1 billion yuan, Wanjilong Precision Circuit Board Project was signed and settled in Huangshi, Hubei

Technical ResourceMore

  1. Research on solar photovoltaic charge controller based on MPPT
  2. Dielectric Resonator Microwave Circuit
  3. Development and performance optimization of wireless charging system for electric vehicles_Ren Xiaofeng
  4. A simple Kalman filter C program
  5. Vehicle thermal system integration
  6. Protues simulation example (8051)-ULN2803.rar
  7. Single resistor sampling PWM deformation signal generation for motor control
  8. Added abnormal analysis when using UART interface
  9. 270 small project pictures sharing (with circuit diagrams)
  10. Design of Switching Power Supplies Handbook

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

About Us Customer Service Contact Information Datasheet Sitemap LatestNews
Index Files: 1398  3  1750  1835  1009  29  1  36  37  21 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号