TSPC750AMGU8LE datasheet, PDF - EEWORLD Datasheet

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TSPC750AMGU8LE: DescriptionRISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360; CategoryThe embedded processor and controller Microcontrollers and processors; File Size679KB，44 Pages; ManufacturerAtmel (Microchip)

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TSPC750AMGU8LE Overview

RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360

TSPC750AMGU8LE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	BGA,
Contacts	360
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	83.3 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B360
length	25 mm
low power mode	YES
Humidity sensitivity level	1
Number of terminals	360
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	3.2 mm
speed	200 MHz
Maximum supply voltage	2.7 V
Minimum supply voltage	2.5 V
Nominal supply voltage	2.6 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

TSPC750AMGU8LE Preview

Features

•

12.4 SPECint95, 8.4 SPECfp95 at 266 MHz (TSPC750A) with 1 MB L2 at 133 MHz

11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A)

488 MIPS at 266 MHz

Selectable Bus Clock (11 CPU Bus Dividers up to 8x)

Typical 4.2 W at 200 MHz, Full Operating Conditions

Nap, Doze and Sleep Modes for Power Savings

Superscalar (3 Instructions per Clock Cycle)

4-GByte Direct Addressing Range

64-bit Data and 32-bit Address Bus Interface

32 KB Instruction and Data Cache

Six Independent Execution Units and Two Register Files

Write-back and Write-through Operations

int

max = 266 MHz

bus

max = 83.3 MHz

Compatible CMOS Input / TTL Output

Description

The TSPC750A and TSPC740A microprocessor (after named 750A/740A) are low-

power implementations of the PowerPC Reduced Instruction Set Computer (RISC)

architecture.

The 750A/740A microprocessors’ designs are superscalar, capable of issuing three

instructions per clock cycle into six independent execution units.

The 740A/750A microprocessors use a 2.6/3.3V CMOS process technology and

maintain full interface compatibility with TTL devices.

The 750A/740A provide four software controllable power-saving modes and a thermal

assist unit management.

The 750A/740A microprocessors have separate 32K byte, physically-addressed

instruction and data caches and differ only in that the 750A features a dedicated L2

cache interface with L2 on-chip tags.

Both are software and bus-compatible with the PowerPC 603

™

and PowerPC 604

™

families, and are fully JTAG compliant.

The TSPC740A microprocessor is pin compatible with the TSPC603e family.

PowerPC

750A/740A RISC

Microprocessor

Family PID8t-

750A/740A

Specification

TSPC750A/740A

G suffix

CBGA255 and CBGA360

Ceramic Ball Grid Array

GS suffix

CI-CBGA255 and CI-CBGA360

Ceramic Ball Grid Array

with Solder Column Interposer (SCI)

Rev. 2128A–HIREL–01/02

Screening

This product is manufactured in full compliance with:

•

CBGA upscreenings based upon ATMEL-Grenoble standards

Full military temperature range (Tc = -55°C,+125°C)

Industrial temperature range (Tc = -40°C, +110°C)

CI-CGA versions of TSPC740A and TSPC750A (planned)

The TSPC750A is targeted for low power systems and supports the following power

management features — doze, nap, sleep, and dynamic power management. The

TSPC750A consists of a processor core and an internal L2 Tag combined with a dedi-

cated L2 cache interface and a 60x bus.

Simplified Block

Diagram

Figure 1.

TSPC750A Block Diagram

Instruction Fetch

Branch Unit

Contr l Unit

Completion

32K ICache

System Unit

Dispatch

BHT/BTIC

GPRs

FXU1

FXU2

Rename

Buffers

LSU

FPRs

Rename

Buffers

FPU

32K DCache

L2 Tags

L2 Cache

BIU

60x BIU

TSPC750A/740A

2128A–HIREL–01/02

TSPC750A/740A

General Parameters

Technology

Die Size

Transistor Count

Logic Design

Packages L2

The general parameters of the 750A/740A are the following:

0.29 mm CMOS, five-layer metal

7.56 mm x 8.79 mm (67 mm

)

6.35 million

Fully-static

740A: Surface mount 255 ceramic ball grid array (CBGA) and column interposer ceramic grid

array CI-CGA without L2interface

750A: Surface mount 360 ceramic ball grid array (CBGA) and column interposer ceramic grid

array CI-CGA with L2 interface

Core Power Supply

I/O Power Supply

2.6V ± 100 mV

3.3V ± 5% V

Except L2 cache interface that is not supported by the PowerPC version, the major fea-

tures implemented in the PowerPC 750A architecture are as follows:

•

Internal L2 cache controller and 4K-entry tags; external data SRAMs

256K, 512K, and 1-Mbyte 2-way set associative L2 cache support

Copy-back or write-through data cache (on a page basis, or for all L2)

64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size

Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg)

synchronous burst SRAMs, and pipelined (reg-reg) late-write synchronous burst

SRAMs

Core-to-L2 frequency divisors of

÷1, ÷1.5, ÷2, ÷2.5,

and

÷3

supported

Four instructions fetched per clock

One branch processed per cycle (plus resolving 2 speculations)

Up to 1 speculative stream in execution, 1 additional speculative stream in fetch

512-entry branch history table (BHT) for dynamic prediction

64-entry, 4-way set associative branch target instruction cache (BTIC) to minimize

branch delay slots

Full hardware detection of dependencies (resolved in the execution units)

Dispatch two instructions to six independent units (system, branch, load/store, fixed-

point unit 1, fixed-point unit 2, or floating-point)

Serialization control (predispatch, postdispatch, execution serialization)

One cycle load or store cache access (byte, half-word, word, double-word)

Effective address generation

Hits under misses (one outstanding miss)

Single-cycle misaligned access within double word boundary

Alignment, zero padding, sign extend for integer register file

Floating-point internal format conversion (alignment, normalization)

Sequencing for load/store multiples and string operations

Store gathering

Cache and TLB instructions

Features

Level 2 (L2) Cache Interface

(not implemented on

TSPC740A)

•

Branch Processing Unit

•

Dispatch Unit

•

Load/Store Unit

•

2128A–HIREL–01/02

•

Fixed-point Units

•

Bus Interface

•

Big- and little-endian byte addressing supported

Misaligned little-endian support in hardware

Fixed-point unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical

Fixed-point unit 2 (FXU2)-shift, rotate, arithmetic, logical

Single-cycle arithmetic, shift, rotate, logical

Multiply and divide support (multi-cycle)

Early out multiply

Compatible with 60x processor interface

32-bit address bus

64-bit data bus

Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,

8x supported

Forwarding control

Partial instruction decode

Support for IEEE-754 standard single- and double-precision floating-point arithmetic

3 cycle latency, 1 cycle throughput, single-precision multiply-add

3 cycle latency, 1 cycle throughput, double-precision add

4 cycle latency, 2 cycle throughput, double-precision multiply-add

Hardware support for divide

Hardware support for denormalized numbers

Time deterministic non-IEEE mode

Executes CR logical instructions and miscellaneous system instructions

Special register transfer instructions

32K, 32-byte line, 8-way set associative instruction cache

32K, 32-byte line, 8-way set associative data cache

Single-cycle cache access

Pseudo-LRU replacement

Copy-back or write-through data cache (on a page per page basis)

Supports all PowerPC memory coherency modes

Non-blocking instruction and data cache (one outstanding miss under hits)

No snooping of instruction cache

128 entry, 2-way set associative instruction TLB

128 entry, 2-way set associative data TLB

Hardware reload for TLBs

4 instruction BATs and 4 data BATs

Virtual memory support for up to 4 hexabytes (2

) of virtual memory

Real memory support for up to 4 gigabytes (2

) of physical memory

Decode

•

Floating-point Unit

•

System Unit

•

Cache Structure

•

Memory Management Unit

•

TSPC750A/740A

2128A–HIREL–01/02

TSPC750A/740A

Testability

•

Integrated Power

Management

•

Integrated Thermal

Management Assist Unit

Reliability and Serviceability

•

LSSD scan design

JTAG interface

Low-power 2.6/3.3V design

Three static power saving modes: doze, nap, and sleep

Automatic dynamic power reduction when internal functional units are idle

On-chip thermal sensor and control logic

Thermal Management Interrupt for software regulation of junction temperature.

Parity checking on 60x and L2 cache buses

Pin Assignments

TSPC740A Package

The pinout of the TSPC740A, 255 CBGA and CI-CGA packages as viewed from the top

surface.

2128A–HIREL–01/02

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