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HY51V64404ASLJC-60

Description
EDO DRAM, 16MX4, 60ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
Categorystorage    storage   
File Size100KB,10 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric View All

HY51V64404ASLJC-60 Overview

EDO DRAM, 16MX4, 60ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

HY51V64404ASLJC-60 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSK Hynix
Parts packaging codeSOJ
package instructionSOJ, SOJ32,.44
Contacts32
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFAST PAGE WITH EDO
Maximum access time60 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
JESD-609 codee0
length20.96 mm
memory density67108864 bit
Memory IC TypeEDO DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals32
word count16777216 words
character code16000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.44
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height3.76 mm
self refreshYES
Maximum standby current0.0003 A
Maximum slew rate0.12 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
HY51V64404A,HY51V65404A
16Mx4, Extended Data Out mode
2nd Generation
DESCRIPTION
This family is a 64M bit dynamic RAM organized 16,777,216 x 4-bit configuration with Extended Data Out mode CMOS
DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process
design allow this device to achieve high performance and low power dissipation. Optional features are access time(50 or
60ns) and refresh cycle(8K ref. or 4K ref.)and package(SOJ or TSOP-ll) and power consumption (Normal or Low power
with self refresh). Hyundai’s advanced circuit design and process technology allow this device to achieve high bandwidth,
low power consumption and high reliability.
FEATURES
Ÿ
Extended data out operation
Ÿ
Read-modify-write capability
Ÿ
Multi-bit parallel test capability
Ÿ
LVTTL(3.3V) compatible inputs and outputs
Ÿ
/CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
Ÿ
Max. Active power dissipation
Speed
50
60
Ÿ
Refresh cycle
Part number
HY51V64404A
1)
HY51V65404A
2)
Refresh
8K
64ms
4K
128ms
Normal
L-part
8K refresh
396mW
324mW
4K refresh
504mW
432mW
Ÿ
JEDEC standard pinout
32-pin plastic SOJ/TSOP-II (400mil)
Ÿ
Single power supply of 3.3
±
0.3V
Ÿ
Early write or output enable controlled write
Ÿ
Fast access time and cycle time
Speed
50
60
tRAC
50ns
60ns
tCAC
13ns
15ns
tHPC
20ns
25ns
1) Normal read / write, /RAS only refresh : 8K cycles / 64ms
/CAS-before-/RAS, Hidden refresh
: 4K cycles / 64ms
2) Normal read / write, /RAS only refresh : 4K cycles / 64ms
/CAS-before-/RAS, Hidden refresh
: 4K cycles / 64ms
ORDERING INFORMATION
Part Name
HY51V64404ATC
HY51V64404ALTC
HY51V64404ASLTC
HY51V65404ATC
HY51V65404ALTC
HY51V65404ASLTC
*SL : Self refresh with low power.
Refresh
8K
8K
8K
4K
4K
4K
Power
Package
32Pin SOJ/TSOP-II
L-part
*SL-part
32Pin SOJ/TSOP-II
32Pin SOJ/TSOP-II
32Pin SOJ/TSOP-II
L-part
*SL-part
32Pin SOJ/TSOP-II
32Pin SOJ/TSOP-II
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
Hyundai Semiconductor
Rev.10/Sep.98
1

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