constructed using three 32K x 8 static RAMs in SOJ packages
mounted onto an epoxy laminate board with pins.
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on
the input/output pins (I/O
0
through I/O
23
) of the device is
written into the memory location specified on the address
pins (A
0
through A
14
).
Reading the device is accomplished by taking the chip select
(CS) and output enable (OE) LOW while write enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear
on the input/output pins.
The input/output pins remain in a high-impedance state unless
the module is selected, outputs are enabled, and write enable
is HIGH.
Functional Description
The CYM1720 is a high-performance 768-kilobit static RAM
module organized as 32K words by 24 bits. This module is
Logic Block Diagram
Pin Configuration
ZIP
Top View
V
CC
I/O
1
I/O
3
I/O
5
I/O
7
GND
A
1
A
3
A
5
A
7
NC
GND
I/O
9
I/O
11
I/O
13
I/O
15
NC
OE
A
9
A
11
A
13
NC
GND
I/O
17
I/O
19
I/O
21
I/O
23
V
CC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
A
0
−
A
14
OE
WE
CS
15
32K x 8
SRAM
8
I/O
0
−
I/O
7
32K x 8
SRAM
8
I/O
8
−
I/O
15
32K x 8
SRAM
8
I/O
16
−
I/O
23
1720–1
V
CC
I/O
0
I/O
2
I/O
4
I/O
6
GND
A
0
A
2
A
4
A
6
CS
NC
I/O
8
I/O
10
I/O
12
I/O
14
GND
WE
A
8
A
10
A
12
A
14
GND
I/O
16
I/O
18
I/O
20
I/O
22
V
CC
1720–2
Selection Guide
1720-15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Shaded area contains preliminary information.
1720-20
20
450
120
1720-25
25
330
60
1720-30
30
330
60
1720-35
35
330
60
15
450
120
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
September 1989 – Revised April 1993
CYM1720
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –55°C to +125°C
Ambient Temperature with
Power Applied............................................... –10°C to +85°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
CYM1720-15, 20
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
Automatic CS
Power-Down Current
[1]
Automatic CS
Power-Down Current
[1]
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
CS < V
IL
Max. V
CC
, CS > V
IH
,
Min. Duty Cycle = 100%
Max. V
CC
, CS > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Test Conditions
V
CC
= Min., I
OH
= – 4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–20
–10
Min.
2.4
0.4
V
CC
0.8
+20
+10
450
120
90
2.2
–0.5
–20
–10
Max.
CYM1720-25, 30, 35
Min.
2.4
0.4
V
CC
0.8
+20
+10
330
60
60
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Shaded area contains preliminary information.
Capacitance
[2]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
35
25
Unit
pF
pF
Notes:
1. A pull-up resistor to V
CC
on the CS input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
2. Tested on a sample basis.
AC Test Loads and Waveforms
481Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
255Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
255Ω
GND
< 5 ns
1720–3
481Ω
3.0V
ALL INPUT PULSES
90%
10%
90%
10%
< 5ns
1720–4
(a)
(b)
Equivalent to:
OUTPUT
THÉ VENIN EQUIVALENT
167Ω
1.73V
2
CYM1720
Switching Characteristics
Over the Operating Range
[3]
1720-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PU
t
PD
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
CS LOW to Power-Up
CS HIGH to Power-Down
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[5]
15
10
10
1
1
10
9
1
3
0
8
0
15
20
12
12
2
2
12
10
2
3
0
8
3
6
0
20
25
20
20
2
5
20
12
2
5
0
10
0
6
3
8
0
25
30
25
25
5
5
25
18
3
5
0
15
3
15
8
0
8
3
20
0
25
35
30
30
5
5
25
18
3
5
0
15
15
15
3
20
10
0
10
5
20
0
30
20
20
3
25
10
0
20
3
20
25
25
3
30
15
0
20
30
30
3
35
18
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1720-20
Min.
Max.
1720-25
Min.
Max.
1720-30
Min.
Max.
1720-35
Min.
Max.
Unit
WRITE CYCLE
[6]
Shaded area contains preliminary information.
Notes:
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
4. At any given temperature and voltage condition, t
HZCS
is less than t
LZCS
for any given device.
5. t
HZOE
, t
HZCS
, and t
LZCE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±500
mV from steady-state voltage.
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CYM1720
Switching Waveforms
Read Cycle No. 1
[7,8]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1720–5
Read Cycle No. 2
CS
[7,9]
t
RC
t
ACS
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
t
LZCS
t
PU
V
CC
SUPPLY
CURRENT
50%
DATA VALID
t
PD
ICC
50%
ISB
1720–6
t
HZOE
t
HZCS
HIGH
IMPEDANCE
Write Cycle No. 1 (WE Controlled)
[6,10]
t
WC
ADDRESS
t
SCS
CS
t
AW
t
SA
WE
t
SD
DATA IN
DATA VALID
t
HZWE
DATA I/O
DATA UNDEFINED
1720–7
t
HA
t
PWE
t
HD
t
LZWE
HIGH IMPEDANCE
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = V
IL
and OE= V
IL
.
9. Address valid prior to or coincident with CS transition LOW.
10. Data I/O will be high impedance if OE = V
IH
.
4
CYM1720
Switching Waveforms
(continued)
[6,10,11]
Write Cycle No. 2 (CS Controlled)
t
WC
ADDRESS
t
SA
CS
t
AW
t
PWE
WE
t
SD
DATA IN
DATA VALID
t
HZWE
DATA I/O
HIGH IMPEDANCE
DATA UNDEFINED
1720–8
t
SCS
t
HA
t
HD
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
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