CL4J-67205V-60 datasheet, PDF - EEWORLD Datasheet

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CL4J-67205V-60: DescriptionFIFO, 8KX9, 60ns, Asynchronous, CMOS, LCC-32; Categorystorage storage; File Size144KB，15 Pages; ManufacturerAtmel (Microchip)

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CL4J-67205V-60 Overview

FIFO, 8KX9, 60ns, Asynchronous, CMOS, LCC-32

CL4J-67205V-60 Parametric

Parameter Name	Attribute value
Maker	Atmel (Microchip)
Parts packaging code	QFJ
package instruction	,
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	60 ns
period time	75 ns
JESD-30 code	S-XQCC-N32
memory density	73728 bit
memory width	9
Number of functions	1
Number of terminals	32
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8KX9
Exportable	NO
Package body material	UNSPECIFIED
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	QUAD

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MATRA MHS

L 67205

9 / 3.3 Volts CMOS Parallel FIFO

Introduction

The L67205 implements a first-in first-out algorithm,

featuring asynchronous read/write operations. The FULL

and EMPTY flags prevent data overflow and underflow.

The Expansion logic allows unlimited expansion in word

size and depth with no timing penalties. Twin address

pointers automatically generate internal read and write

addresses, and no external address information are

required for the MHS FIFOs. Address pointers are

automatically incremented with the write pin and read

pin. The 9 bits wide data are used in data communications

applications where a parity bit for error checking is

necessary. The Retransmit pin reset the Read pointer to

zero without affecting the write pointer. This is very

useful for retransmitting data when an error is detected in

the system.

Using an array of eigh transistors (8 T) memory cell and

fabricated with the state of the art 1.0

µm

lithography

named SCMOS, the L 67205 combine an extremely low

standby supply current (typ = 1.0

µA)

with a fast access

time at 55 ns over the full temperature range. All versions

offer battery backup data retention capability with a

typical power consumption at less than 5

µW.

For military/space applications that demand superior

levels of performance and reliability the L 67205 is

processed according to the methods of the latest revision

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

Features

First-in first-out dual port memory

Single supply 3.3

0.3 volts

8192

9 organisation

Fast access time

55, 60, 65 ns, commercial, industrial military

and automotive

Wide temperature range :

– 55

°C

to + 125

°C

67205L low power

67205V very low power

Fully expandable by word width or depth

Asynchronous read/write operations

Empty, full and half flags in single device mode

Retransmit capability

Bi-directional applications

Battery back-up operation 2 V data retention

High performance SCMOS technology

Rev. C (10/11/94)

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